On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

Abstract

This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency ( f t ) of the device. For a balanced design, our simulations indicate an n-p-n device with an f t of 812 GHz and an f max of 1.08 THz; and a p-n-p device with an f t of 635 GHz and an f max of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is ∼0.03 mA-roughly 100 times lower than commercial vertical heterojunction bipolar transistors.

Comparative Study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI

“…The device with the Si-0.3Ge-Si configuration exhibits a peak gain of 8.4 × 10 5 , the device with the Si-graded-Si configuration exhibits a peak gain of 5.5 × 10 5 , and the device with the Si-Ge-Si configuration exhibits a peak gain of 5.1 × 10 5 @ I C ≈ 3.0 μA/μm. The values in the gain also show that our novel 3SCP SLHBT design exhibit better current gain than the lateral SiGe HBT with a partially depleted base …”

“…The values in the gain also show that our novel 3SCP SLHBT design exhibit better current gain than the lateral SiGe HBT with a partially depleted base. 6 To explain the above observation in the current gain plot, let us break the data in two regions: (a) the lower I C range where Si-0.3Ge-Si configuration shows higher current gain, which is the range after which the current gain falls off sharply, and (b) the higher I C range, where the device with pure Ge as the base show dominance over the other two. This range is the high injection regime where current gain starts to roll off.…”

“…Many advantages for symmetric lateral bipolar transistors on SOI, which include CMOS compatible process flow, improved performance such as higher gains and higher cutoff frequencies, have made this device a good choice for extremely low power mixed signal/analog applications. − …”

“…In the cCP design − and in our novel 3SCP design, the base metal electrode is directly deposited above the active device layer. Above the management of the thermal budget, these designs would have an additional advantage over the symmetric lateral bipolar transistors − and the lateral symmetric transistor with electrostatic polarity control approach as a result of the absence of the polysilicon-doped extrinsic base placed above the intrinsic base …”