On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications

Sánchez, Fermín; Álvarez, Mauricio A.; Salamf, E.; Ramírez, Alex; Valero, Mateo

doi:10.1109/ispass.2005.1430571

Cited by 5 publications

(4 citation statements)

References 19 publications

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“…At a high level, SVectors exploit two dimensional DLP, as done by traditional SIMD array processors [Hwang 1993], MOM Sanchez et al 2005], and CSI [Cheresiz et al 2005]. This is because SVectors are, in turn, composed of small vectors (SIMD).…”

Section: Other Architecturesmentioning

confidence: 99%

Alp

Sasanka

Adve

et al. 2007

ACM Trans. Archit. Code Optim.

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The real-time execution of contemporary complex media applications requires energy-efficient processing capabilities beyond those of current superscalar processors. We observe that the complexity of contemporary media applications requires support for multiple forms of parallelism, including ILP, TLP, and various forms of DLP, such as subword SIMD, short vectors, and streams. Based on our observations, we propose an architecture, called ALP, that efficiently integrates all of these forms of parallelism with evolutionary changes to the programming model and hardware. The novel part of ALP is a DLP technique called SIMD vectors and streams (SVectors/SStreams), which is integrated within a conventional superscalar-based CMP/SMT architecture with subword SIMD. This technique lies between subword SIMD and vectors, providing significant benefits over the former at a lower cost than the latter. Our evaluations show that each form of parallelism supported by ALP is important. Specifically, SVectors/SStreams are effective, compared to a system with the other enhancements in ALP. They give speedups of 1.1 to 3.4X and energy-delay product improvements of 1.1 to 5.1X for applications with DLP.

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Section: Other Architecturesmentioning

confidence: 99%

Alp

Sasanka

Adve

et al. 2007

ACM Trans. Archit. Code Optim.

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“…SODA and AnySP consist of a single scalar and SIMD integer pipelines that target software defined radio. Matrix-oriented SIMD instruction extensions for microprocessors have been developed as well [6]. Logic cell densities have facilitated soft vector processors on FPGAs [7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

ASIC Design of Shared Vector Accelerators for Multicore Processors

Beldianu

Ziavras

2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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--Vector coprocessor (VP) resources are often underutilized due to the lack of sustained DLP (data-level parallelism) or the presence of vector-length variations in application code. Our work is motivated by: a) the omnipresence of vector operations in high-performance scientific and embedded applications; b) the need for performance and energy efficiency; and c) applications that must often handle various vector sizes. Our design for VP sharing in multicores enhances performance while maintaining low area and energy costs. Our 40nm ASIC design yields 16.66 GFLOPs/Watt. Also, a detailed clock and power gating analysis further proves the viability of our approach.

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“…Vector microprocessors have been shown to be more effective in embedded media applications than superscalar and VLIW processors [1]. Also, a 2-dimensional (matrix) SIMD extension was developed in [13]. Due to recent advances in programmable devices that have substantially increased their logic cell densities, some FPGA-based soft vector processors have been proposed as well [6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%