On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

Abstract

In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

Chaotic Oscillations in Cascoded and Darlington-Type Amplifier Having Generalized Transistors

“…For each run of Monte-Carlo, the generated waveforms (state variables) undergo the test for the presence of chaotic patterns. In the case of active devices used in the chaotic oscillators, tolerance analyses make sense especially for CMOS implementations of the chaotic system, usually combined with process-voltage-temperature analysis [46].…”

The Automatic Design of Multimode Resonator Topology with Evolutionary Algorithms

“…Among the existing optimization methods for continuous search spaces, the evolutionary algorithms are considered as the most efficient global optimization techniques, as long as they are capable of finding global optimum even for complicated landscapes due to their population-based structure and randomized search. Various evolutionary algorithms are a popular and efficient tool for microelectronic device design [64][65][66] as well as data processing for evaluation of their quality [67,68]. Therefore, in this study, two evolutionary optimizers were considered: the differential evolution algorithm and the genetic algorithm (GA).…”

Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area

“…The Artificial intelligence (AI) evolutionary algorithms (EAs) are used to successfully optimize the analog CMOS ICs [73] [74]. EAs are classified into two main categories: I) a priori: characterized by the definition of the desired specifications before carrying out the optimization process; II) a posteriori: can provide several potential solutions that meet the desired specifications.…”

“…EAs are classified into two main categories: I) a priori: characterized by the definition of the desired specifications before carrying out the optimization process; II) a posteriori: can provide several potential solutions that meet the desired specifications. However, designers often use Pareto techniques to choose the solution that best meets their needs after the optimization process [73] [74].…”