On the speedup required for work-conserving crossbar switches

Krishna, P.; Patel, N.S.; Charny, A.; Simcoe, Robert J.

doi:10.1109/iwqos.1998.675243

Cited by 48 publications

(21 citation statements)

References 16 publications

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“…It is widely held that the O(N 3 ) computational complexity of maximum weighted matching is overly burdensome for implementation on a slot-by-slot basis in practical systems operating at high rates [1]. Many practitioners resort to suboptimal matching algorithms in conjunction with speedup to provide optimal throughput performance.…”

Section: Introductionmentioning

confidence: 99%

Greedy weighted matching for scheduling the input-queued switch

Brzezinski

Modiano

2006

2006 40th Annual Conference on Information Sciences and Systems

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Section: Introductionmentioning

confidence: 99%

Greedy weighted matching for scheduling the input-queued switch

Brzezinski

Modiano

2006

2006 40th Annual Conference on Information Sciences and Systems

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“…Therefore, typically in CIOQ switches a central scheduler uses fixed sized packets (i.e., cells) as the units of data to be transferred between inputs and outputs. LOOFA [4] is a promising scheduler for CIOQ switch that with a speedup of two makes a CIOQ cell switch network like ATM work-conserving. At the same time, there is no known efficient scheduling algorithm for handling variable-length packet in a traditional CIOQ switch where the cells belonging to a single packet must be sent contiguously.…”

Section: Introductionmentioning

confidence: 99%

LOOFA-PB: A Modified LOOFA Scheduler for Variable-Length Packet Switching

Shiravi

Min

2007

2007 IEEE International Conference on Communications

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The LOOFA algorithm is a cell-based scheduler for CIOQ crossbar switches that can guarantee the work-conserving property in a cell-based switch if the crossbar switch works twice as fast as the line rate (speedup of two). Unfortunately, the cell based LOOFA algorithm is not work-conserving for variablelength packet switches because it interleaves the cells from different inputs to a particular output and does not necessarily serve cells belonging to a packet contiguously. Thus, the cells belonging to a variablelength packet must be reassembled at the output port before the packet can be transmitted. This requires a large buffer at the output stage, and causes extra delays. PLF, which is another suggested scheduling algorithm for variable-length packet switches, has its own limitations. PLF must use a considerable amount of memory at every crosspoint of the buffered crossbar, making the overall complexity high. In this paper we examine the work conserving property of the LOOFA and the PLF algorithms in variable-length packet switches and propose a packet-based version of the LOOFA (called the LOOFA-PB) for variable-length packets. The proposed algorithm is a (L max /2)-workconserving algorithm and does not need a buffered crossbar or a speedup greater than two. In addition, the LOOFA-PB algorithm eliminates the need for reassembly and serves packets contiguously. As a result, it reduces the overall packet delay. Finally, eliminating the SAR functionality from the algorithm results in a smaller die size when implemented in an ASIC, and cheaper cost.

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“…arrivals (uniform or nonuniform) [2], [3]. Because of the high complexity of MWM, maximal matching algorithms [4], [5], [6], [7], [8], [9], [10], [13] have been proposed to approximate MWM, but they cannot guarantee 100% throughput without speedup. Recently, some matching algorithms [11], [12], [13], [14], which are not MWM but can still guarantee 100% throughput without speedup have been devised.…”

Section: Introductionmentioning

confidence: 99%

NXG06-5: Packet Delay-Aware Scheduling in Input Queued Switches

Li¹,

Panwar²,

Chao³

et al. 2006

IEEE Globecom 2006

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Virtual Output Queuing is widely used by highspeed packet switches to overcome head-of-line blocking. This is done by means of matching algorithms. In fixed-length VOQ switches, variable-length IP packets are segmented into fixedlength cells at the inputs. When a cell is transferred to its destination output, it will stay in the reassembly buffer and wait for the other cells of the same packet before the entire packet can depart the system. The delay a packet suffers in the system includes the waiting time in the VOQ, the widely studied cell delay, and the waiting time at the output reassembly buffer, the reassembly delay often ignored in many papers. Among all existing matching algorithms, Maximum Weight Matching (MWM) has the lowest average cell delay. In this paper, we investigate the average packet delay, one of the key performance measure for an input buffered packet switch. A new class of matching algorithms, PDA-MWM, is defined and proved to be stable under all admissible traffic. Three PDA-MWM matching algorithms are studied by simulation. We show that, in order to achieve low packet delay, there is a tradeoff between the cell delay performance and the reassembly delay performance. If both of them are carefully considered, a matching scheme can greatly reduce the packet delay as compared to MWM.

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On the speedup required for work-conserving crossbar switches

Cited by 48 publications

References 16 publications

Greedy weighted matching for scheduling the input-queued switch

Greedy weighted matching for scheduling the input-queued switch

LOOFA-PB: A Modified LOOFA Scheduler for Variable-Length Packet Switching

NXG06-5: Packet Delay-Aware Scheduling in Input Queued Switches

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