On the Stability of Charge-Pump Phase-Locked Loops

Homayoun, Aliakbar; Razavi, Behzad

doi:10.1109/tcsi.2016.2537823

Cited by 27 publications

(4 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…While for the discrete time model ( 14) the limit cycles of low-periods without overload can be easily found analytically (see, e.g. [36]), the computing of limit cycles in the case Stable (red) and unstable (blue) period-3 limit cycles (hidden oscillations). Turquoise: overload; black curves: separation of the smoothness regions.…”

Section: The Pull-in Range and Non-local Analysismentioning

confidence: 99%

Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges

Kuznetsov

Matveev

Yuldashev

et al. 2021

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

In this paper a fairly complete mathematical model of CP-PLL, which reliable enough to serve as a tool for credible analysis of dynamical properties of these circuits, is studied. We refine relevant mathematical definitions of the hold-in and pull-in ranges related to the local and global stability. Stability analysis of the steady state for the charge-pump phase locked loop is non-trivial: straight-forward linearization of available CP-PLL models may lead to incorrect conclusions, because the system is not smooth near the steady state and may experience overload. In this work necessary details for local stability analysis are presented and the hold-in range is computed. An upper estimate of the pull-in range is obtained via the analysis of limit cycles. The study provided an answer to Gardner's conjecture on the similarity of transient responses of CP-PLL and equivalent classical PLL and to conjectures on the infinite pull-in range of CP-PLL with proportionally-integrating filter.

show abstract

Section: The Pull-in Range and Non-local Analysismentioning

confidence: 99%

Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges

Kuznetsov

Matveev

Yuldashev

et al. 2021

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…Another benefit of the two-stage configuration is that although the band-limiting capacitor needs to be broken up into K units to accommodate all phases it is an explicit capacitor and unlike the single-stage configuration it does not rely on the precise control/matching of parasitic capacitance to determine the pole location. Moreover charge pump circuits and the associated dynamics have been studied extensively in PLL circuits [27] and can easily be applied here. That said, it can be concluded that the two-stage ROF should be used in scenarios when the output and bandwidth characteristics need to be precise and the single-stage ROF should be applied when focus lies with performing asynchronous computation with diminished requirements.…”

Section: B Two-stage Rofmentioning

confidence: 99%

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Leene

Constandinou

2017

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems

show abstract

“…Since they are based on an early linearization, nonlinear and non-ideal effects are not considered [11]. However, it is essential to take them into account for a robust design, since they affect the stability, frequency purity and transient dynamic behavior [12], [13]. Additionally, the validity of these modeling approaches is limited to the domain close to the operation point, discarding them for transient pull-in predictions which are essential when considering frequency synthesis.…”

Section: Introductionmentioning

confidence: 99%

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Guerin,

Haddad,

Sazzad

et al. 2023

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

View full text Add to dashboard Cite

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

show abstract

On the Stability of Charge-Pump Phase-Locked Loops

Cited by 27 publications

References 18 publications

Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges

Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Contact Info

Product

Resources

About