2019
DOI: 10.1109/tns.2019.2898894
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On the Susceptibility of SRAM-Based FPGA Routing Network to Delay Changes Induced by Ionizing Radiation

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Cited by 7 publications
(4 citation statements)
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“…Fig. 1 shows the topology of a CLB and interconnect (INT) tiles in Xilinx 7-Series APSoCs [3], [5]. In this scheme, the planar SM has an injective mapping where each input node on the right side is connected to only one node on its left side.…”
Section: A Logic and Interconnect Tiles Resourcesmentioning
confidence: 99%
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“…Fig. 1 shows the topology of a CLB and interconnect (INT) tiles in Xilinx 7-Series APSoCs [3], [5]. In this scheme, the planar SM has an injective mapping where each input node on the right side is connected to only one node on its left side.…”
Section: A Logic and Interconnect Tiles Resourcesmentioning
confidence: 99%
“…It is noted that these interconnects are not valid for the PS side cause it is made of the multi-core microcontroller cores with dedicated interconnection network for itself and is out of the focus in this paper. Interconnects linking the Wilton SMs are categorized as follows [3], [5]:…”
Section: B Interconnect Types Available In 7-series Fpgasmentioning
confidence: 99%
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“…Further, “when a source node wants to transfer the data to the sink node, it (source node) collects the position of the sink node and directly transfers the data to the ring structure without passing it to multiple neighbours.” 3,33–35 This mechanism might reduce the overhead of data transmission 36–39 . Further, based on the sink movement, the ring structure can be altered; therefore it is applicable for time‐sensitive application 40–43 …”
Section: Introductionmentioning
confidence: 99%