On the test of a COTS-based system for space applications

Carbonara, Sara; Firrincieli, Andrea; Reorda, M. Sonza; Meß, Jan-Gerd

doi:10.1109/iolts.2018.8474085

Cited by 2 publications

(7 citation statements)

References 3 publications

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“…For this reason, in [7] we proposed an approach, which aims at partly automating the safe faults identification process taking into account all the constraints coming from the application scenario, including the application software to be run by the CPU. Some preliminary results coming from the application of the same method to the OR1200 CPU have been reported in [19]. In this paper, we improve the procedure used in [7] and [19] and extend the work reported in [23] to peripheral modules, not necessarily CPU only.…”

Section: Safe Faults Identificationmentioning

confidence: 83%

“…Some preliminary results coming from the application of the same method to the OR1200 CPU have been reported in [19]. In this paper, we improve the procedure used in [7] and [19] and extend the work reported in [23] to peripheral modules, not necessarily CPU only. The improved method is now able to identify a larger number of safe faults, thanks to a mechanism allowing to exploit the power of a commercial ATPG tool.…”

Section: Safe Faults Identificationmentioning

confidence: 83%

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Improved Test Solutions for COTS-Based Systems in Space Applications

Cantoro

Carbonara

Floridia

et al. 2019

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

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In order to widen the spectrum of available products, companies involved in space electronics are exploring the possible adoption of COTS components instead of space-qualified ones. However, the adoption of COTS devices and boards requires suitable solutions able to guarantee the same level of dependability. A mix of different solutions can be considered for this purpose. Test techniques play a major role, since they must guarantee that a high percentage of permanent faults can be detected (both at the end of the manufacturing and during the mission) while matching several constraints in terms of system accessibility and hardware complexity. In this paper we focus on the test of the electronics used within launchers, and outline an approach based on Software-based Self-test. The proposed solutions are currently being adopted within the MaMMoTH-Up project, targeting the development of an innovative COTSbased system to be used on the Ariane5 launcher. The approach aims at testing both the OR1200 processor and the different peripheral modules adopted in the system, while providing new techniques for the identification of safe faults. The results show the effectiveness and current limitations of the method, also including a comparison between functional and structural test approaches.

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Section: Safe Faults Identificationmentioning

confidence: 83%

Section: Safe Faults Identificationmentioning

confidence: 83%

Improved Test Solutions for COTS-Based Systems in Space Applications

Cantoro

Carbonara

Floridia

et al. 2019

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

Self Cite

View full text Add to dashboard Cite

show abstract

“…To perform the same step, in this paper we resort to an ATPG tool, so that a larger number of safe faults can be identified, taking into account the constraints on the input signals of the combinational logic. This allowed us to increase by about 3% the number of safe faults identified by this step with respect to the results presented in [19]. The usage of a commercial tool also makes the applicability of the proposed method easier.…”

Section: B Safe Faults Identificationmentioning

confidence: 91%

“…For this reason, in [7] we recently proposed an approach, which aims at partly automating the safe faults identification process taking into account all the constraints coming from the application scenario, including the application software to be run by the CPU. Some preliminary results coming from the application of the same method to the OR1200 CPU have been reported in [19].…”

Section: B Safe Faults Identificationmentioning

confidence: 99%

“…The reader should note that in [7] and [19] the last step was performed resorting to a simple topological analysis of the effects of the fixed values in the combinational logic: the analysis identified for each gate the possible untestable faults caused by any fixed value on the inputs of the fault. Hence, the analysis was only able to identify redundant signals or gates in the circuit leading to untestable faults.…”

Section: B Safe Faults Identificationmentioning

confidence: 99%

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An analysis of test solutions for COTS-based systems in space applications

Cantoro

Carbonara

Floridia

et al. 2018

2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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One of the current trends in space electronics is towards considering the adoption of COTS components, mainly to widen the spectrum of available products. When substituting space-qualified components with COTS ones a major challenge lies in guaranteeing the same level of reliability. To achieve this goal, a mix of different solutions can be considered, including effective test techniques, able to guarantee a high level of permanent fault coverage while matching several constraints in terms of system accessibility and hardware complexity. In this paper, we describe an approach based on Software-based Self-test, which is currently being adopted within the MaMMoTH-Up project, targeting the development of an innovative COTS-based system to be used on the Ariane5 launcher. The approach aims at testing the OR1200 processor adopted in the system, combined with new and effective techniques for identifying the safe faults. Results also include a comparison between functional and structural test approaches.I.

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On the test of a COTS-based system for space applications

Cited by 2 publications

References 3 publications

Improved Test Solutions for COTS-Based Systems in Space Applications

Improved Test Solutions for COTS-Based Systems in Space Applications

An analysis of test solutions for COTS-based systems in space applications

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