On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs

Abstract

Over the past few years, several self-calibration methodologies have proven their efficiency to calibrate analog and radio-frequency circuits against process variations. Specifically, statistical techniques based on machine-learning have been proposed to recover yield loss and even enhance circuit performances. In addition, these techniques enable to calibrate circuits after a single performance test, i.e. in one-shot. However, towards fully-integrated calibration techniques, the inference part of the machine learning algorithm needs to be performed as energyefficiently as possible to reduce calibration cost to a minimum. Following the path of resource-efficient machine learning, this work explores an alternative to state-of-the-art Neural Network based statistical techniques. Specifically, we investigate the opportunities of using Bayesian Networks for resource-efficient onchip statistical calibration of analog/RF circuits. Results will show that several improvements can be achieved using Bayesian Networks: (a) provide a comprehensive calibration framework with explicit relationships between parameters (b) demonstrate similar prediction accuracies that neural networks (c) optimize across several performance parameters with a single network and in a single query and (d) enable a more energy-efficient hardware implementation. The proposed self-calibration algorithm is applied to a low-noise amplifier fabricated with IBM's 130nm CMOS process, leading to a significant reduction in the number of operations required to obtain the best tuning knob setting.(1) With off-chip post-manufacturing phase (2) With a fully on-chip procedure Off-line training phase On-line (and/or on-chip) phase Optimal Tuning Knobs BUILT-IN TEST

Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations

“…7. Illustration of the classification process boundaries following equation (1). In the frame of this paper, it is assumed that the simulated dies are on a single wafer and thus the test boundaries depend on the entire simulated population.…”