On the use of embedded debug features for permanent and transient fault resilience in microprocessors

Portela-García, M.; Grosso, M.; Gallardo-Campos, M.; Reorda, M. Sonza; Entrena, Luis; García-Valderas, M.; López-Ongil, C.

doi:10.1016/j.micpro.2012.02.013

Cited by 24 publications

(21 citation statements)

References 23 publications

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“…Code size overhead is smaller or similar. The approaches differ in the fault injection techniques: [30] uses software fault injection, while [8], [14] and [16] inject faults directly in the signals of the microprocessor VHDL code. In contrast, we inject into every node of the final synthesized netlist and consider the real delays as estimated by the synthesis tool.…”

Section: Resultsmentioning

confidence: 99%

“…This may pose some difficulties, particularly if cache memories are used, because the cache interface is usually critical or may not be available. The use of debug infrastructures has recently been proposed as a alternative way to observe microprocessor execution [16]. Debug infrastructures are intended to support debugging during the development phase, and are very common in modern microprocessors.…”

Section: Background and Related Workmentioning

confidence: 99%

“…On the other hand, they can provide internal access to the microprocessor without disturbing it. In [16] the debug infrastructure is used to get the most relevant information of the execution combined with time or hardware redundancy. However, this approach requires at least a full duplication of the execution of the program.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The information that can be obtained from the trace interface usually includes the value of the program counter, the operation code (opcode), instruction results, load data and store data. A detailed analysis of the trace interface for several processors can be found in [16]. In comparison, CFC techniques that use a watchdog processor observe the processor operation through the microprocessor or system bus.…”

Section: Hybrid Hardening Approachmentioning

confidence: 99%

See 3 more Smart Citations

Efficient mitigation of data and control flow errors in microprocessors

Parra¹,

Lindoso²,

Portela³

et al. 2013

2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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Abstract-The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.

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Section: Resultsmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Section: Hybrid Hardening Approachmentioning

confidence: 99%

See 2 more Smart Citations

Efficient mitigation of data and control flow errors in microprocessors

Parra¹,

Lindoso²,

Portela³

et al. 2013

2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

View full text Add to dashboard Cite

show abstract

“…Microprocessor specific techniques introduce system level redundancy by using multiple processors, coprocessors or specialized system modules [12]- [15]. In particular, the reuse of debug infrastructures has recently been proposed [16]. Debug infrastructures are intended to support debugging during the development phase, and are very common in modern microprocessors.…”

Section: Introductionmentioning

confidence: 99%