On the use of static branch prediction to reduce the worst-case execution time of real-time applications

Introduction: Accurate branch prediction technique has become compulsory in the superscalar and deep pipeline processors. The conditional instructions can break the continuous flow of execution in the pipeline stages, thereby decreasing processor performance. Discussion: This paper highlights the concept of branch prediction, some issues and challenges, and techniques for improving processor performance. Further, this paper also presents the role of branch prediction in different processors and their features. Conclusion: The concept of the branch prediction used in parallel processors to enhance the execution speed of the conditional branch instructions and improve the processor's performance is highlighted in this paper. Further, this paper highlights the branch predictor techniques with their features and presents the challenges, issues, and future techniques related to the branch prediction.

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On the use of static branch prediction to reduce the worst-case execution time of real-time applications

Cited by 2 publications

References 17 publications

Implemented Static Branch Prediction Schemes for the Parallelism Processors

Implemented Static Branch Prediction Schemes for the Parallelism Processors

Towards the Improvement of Branch Instructions Identification in High- Performance Processors: Issues, Challenges and Techniques

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