On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

Wong, Hei; Kakushima, Kuniyuki

doi:10.3390/nano12101739

Cited by 17 publications

(12 citation statements)

References 26 publications

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“…Ge, and Ge-related alloys such as SiGe and GeSn, are becoming major key players in the finFET and Gate-All-Around (GAA) FET industries 1 – 8 due primarily to their higher attainable electron and hole mobilities relative to Si 9 . The integration of Ge as the main channel material in the form of single crystal nanowires and nanosheets for finFET 10 and GAA-based devices 1 , 5 , 6 , 11 will inevitably expose low-index surfaces such as (001), (110) and (111) at the interfaces between the channel, dielectric (oxide) gates, and source/drains contacts, given their relatively low surface energies. On another hand, device performance utilising these nanostructures are significantly affected by the crystal orientation of Ge.…”

Section: Introductionmentioning

confidence: 99%

Band-offsets scaling of low-index Ge/native-oxide heterostructures

Ong,

Tok

2024

Sci Rep

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We investigate, through XPS and AFM, the pseudo layer-by-layer growth of Ge native oxide across Ge(001), (110) and (111) surfaces in ambient environment. More significantly, our study reveals a universal set of valence and conduction band offset (VBO and CBO) values observed for Ge(001), Ge(110), and Ge(111) surfaces as a function of Ge-oxide concentration. We find that the band offsets appear to be the same across these low-index Ge surfaces i.e., for Ge-oxide/Ge heterostructures with the same Ge-oxide overlayer concentration or thickness. In contrast, different oxidation rates for Ge(001), Ge(110), and Ge(111) surfaces were observed, where the oxidation rate is fastest for Ge(001), compared to Ge(110) and Ge(111). This can be attributed to the different number of unsatisfied Ge dangling bonds (2 vs 1) associated to the respective ideal Ge surface in forming Ge-oxide. Thus, at any given oxidation time, the oxide concentration or thickness for each type of low index Ge surface will be different. This in turn will lead to different band offset value observed for each type of Ge surface. More significantly, we show that while oxidation rates can differ from different Ge surface-types, the band offset values can be estimated simply based on the Ge-oxide concentration regardless of Ge surface type.

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Section: Introductionmentioning

confidence: 99%

Band-offsets scaling of low-index Ge/native-oxide heterostructures

Ong,

Tok

2024

Sci Rep

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“…Even though the ~0.5 nm EOT is possible with high-dielectric constant (high-k) metal oxide deposited with the most advanced fabrication facility [ 3 , 14 ], the high-k/Si interfaces were found to have much higher interface state density, and the interface is less thermally stable, exhibiting a higher degree of surface roughness. In studying the sizing effect of the nanowire transistor, significant mobility degradation and some anomalous behaviors were found as the sizes of the nanowire were reduced to smaller than 10 nm [ 15 ]. In this report, we conduct a comprehensive study on the temperature-dependent current–voltage characteristics for different sizes of nanowire transistors and discover a new current conduction mechanism between the source and drain.…”

Section: Introductionmentioning

confidence: 99%

Poole–Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor

Wong

Kakushima

2023

Nanomaterials

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This work reports, for the first time, the phenomenon of lateral Poole–Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current–voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole–Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole–Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires.

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“…Though there are extensive research revolving around the advancement of FinFETs in mitigating short channel effects (SCEs), reports in highlighting the advantageous characteristics of the GAA NWFETs are relatively lacking. The unique structure of the GAA NWFET in which the channel is surrounded by gate all around it -thus the name "Gate-All-Around" -provides the transistor with high surface-to-volume ratio [3] and this con guration also gives a better gate controllability over the channel as compared to other advanced MOSFET con gurations such as the FinFET. In terms of scalability, the nanosheet dimensions are easier to be sized [4] to meet speci c performance requirements.…”

Section: Introductionmentioning

confidence: 99%

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

Yau

Hatta

Wahab

et al. 2022

Preprint

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Gate-all-around nanowire field-effect transistor (GAA NWFET) is a viable alternative to reduce short channel effects. A 3D model of the GAA NWFET was explored by studying the effect of process parameters such as nanowire materials, gate oxide materials and high-κ coverage angles on vital transistor performance metrices specifically threshold voltage, leakage current, current ratio, subthreshold swing (SS) and drain induce barrier lowering (DIBL). It has been observed that the nanowire material of InP provides the lowest threshold voltage and highest drive current. Gate oxide material of HfO2 showed improved leakage current by 88.39%, current ratio by 1439.63%, SS by 24.16% and DIBL by 13.11% relative to the conventional NWFET with SiO2 gate oxide. Moreover, as the high-κ dielectric (HfO2) covers the gate oxide over the channel region, the gate electrostatic control over the channel region increases, thus reducing SS to an ideal value. An exhaustive Taguchi Method with Conceptual Signal-To-Noise Ratio Approach and Pareto Analysis of Variance optimization was conducted to determine the optimal design for high current ratio and low threshold voltage. This work inherently provides a framework in designing an optimized GAA NWFET by considering the device’s highest to lowest domineering design factors in affecting its performance matrices.

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On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

Cited by 17 publications

References 26 publications

Band-offsets scaling of low-index Ge/native-oxide heterostructures

Band-offsets scaling of low-index Ge/native-oxide heterostructures

Poole–Frenkel (PF)-MOS: A Proposal for the Ultimate Scale of an MOS Transistor

Process variations and short channel effects analysis in gate-all-around nanowire field-effect transistor using a statistical Taguchi-Pareto ANOVA framework

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