On the yield of VLSI processors with on-chip CPU cache

Abstract

ÐYield enhancement through the acceptance of partially good chips is a well-known technique [1], [2], [3]. In this paper, we derive a yield model for singlechip VLSI processors with partially good on-chip cache. Also, we investigate how the yield enhancement of VLSI processors with on-chip CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area, and various manufacturing process parameters as defect densities and the fault clustering parameter. One of the main conclusions is that the maximum effective yield is achieved by accepting as good, caches with a very small number of faulty cache blocks. One of the main conclusions is that the maximum effective yield is achieved by accepting as good, processor chips containing caches with a very small number of faulty cache blocks. Index TermsÐFault tolerance, on-chip CPU caches, partially good chips, yield enhancement.

On-Line Failure Detection and Confinement in Caches

“…Offline mechanisms have been extended to perform tests without any ATE [19], but they are still focused on offline testing at fabrication to prevent faulty processors to be shipped. Some works have shown that slightly defective processors can be also shipped for yield increase [16,25]. Although off-line testing mechanisms can be used for on-line testing, they may miss a significant number of faults that may show up intermittently.…”

An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip

“…However, given the trend towards the use of a sophisticated network-on-chip as communication subsystem among the intellectual property cores (IPs) of the SoC [10]- [12], it is foreseeable that many defect-tolerant designs will not have such a simple structure. Evaluating the yield of those defect-tolerant SoCs is far from being a trivial task, mainly because of the fact that realistic defect models have clustering [13] and, thus, introduce dependencies among the failed states of the components of the system (see, for instance, [9] and [14]). A combinatorial method for the evaluation of the functional yield of defect-tolerant SoCs has already been developed [15].…”

Combinatorial methods for the evaluation of yield and operational reliability of fault-tolerant systems-on-chip

“…However, many fault-tolerant designs do not have a regular structure, particularly those using a sophisticated network-on-chip as a communication subsystem among the intellectual property cores (IPs) [4]. Computing the yield and operational reliability of such systemson-chip is difficult, mainly because the fact that realistic defect distributions have clustering [8,14,15,16,17,19] and, thus, introduce dependencies among the initial failed states of the components of the system (see, for instance, [19,28]). Simulation is an approach which is not severely limited by the complexity of the system, but tends to be expensive and does not provide strict error control.…”