Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)
DOI: 10.1109/essderc.2003.1256906
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One time programming (OTP) with Zener diodes in CMOS processes

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Cited by 6 publications
(5 citation statements)
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“…Moreover, the zapping process has to be efficient, thus providing a stable and low resistive zapped device. In contrast to previous works [2], the writing times in present applications are below the microsecond range [1], thus preventing the diffusion of metal atoms into the mono-crystalline Silicon from anode and cathode contacts. This implies that the resistance of the zapped device is governed by the Silicon melting rather than the metal diffusion process.…”
Section: Introductionmentioning
confidence: 90%
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“…Moreover, the zapping process has to be efficient, thus providing a stable and low resistive zapped device. In contrast to previous works [2], the writing times in present applications are below the microsecond range [1], thus preventing the diffusion of metal atoms into the mono-crystalline Silicon from anode and cathode contacts. This implies that the resistance of the zapped device is governed by the Silicon melting rather than the metal diffusion process.…”
Section: Introductionmentioning
confidence: 90%
“…In order to improve the zapping control at low zapping currents, the second part of the paper proposes a new Zener structure. This new Zener structure has been fabricated by surrounding the conventional Zener design [1] with a deep insulator trench. Combining measurement and TCAD simulation, it is demonstrated that the trench thermal barrier modifies the electrothermal evolution of the zapping process thus being of paramount importance to optimize the efficiency of the zapping.…”
Section: Introductionmentioning
confidence: 99%
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“…A shunt regulator can be used to model the regulator in the simulation (for example, based on a Zener diode). Although lateral Zener diodes can be implemented in standard CMOS processes [56], the shunt regulator is often implemented with transistors. However, all topologies are based on the same principle, which involves reducing the shunt resistance of a bypass transistor when the input voltage is below the desired output voltage.…”
Section: B Nfc Tag Ic Modelmentioning
confidence: 99%
“…These voltages have to be processed with special care to avoid breakdown of other junctions. In CMOS, a lateral zener diode can be constructed from adjacent n + and p + diffusions [23].…”
Section: Non-volatile Memory Technologymentioning
confidence: 99%