The capacitance monitoring is one of the important issues for the MMC to obtain high reliability. Since the pulse-width modulation (PWM) is usually implemented in the Field Programmable Gate Array (FPGA), the produced precise switching states in the FPGA cannot be directly access by the top Digital Signal Processor (DSP) controller, which poses challenges on the existing capacitance monitoring methods based on the precise switching states of the MMC. This paper presents a submodule (SM) capacitance monitoring strategy for the MMC with a simple algorithm, where the fundamental frequency components of the SM capacitor voltage and current are extracted to estimate the SM capacitance based on reference, but not the precise switching states. The proposed scheme not only simplifies the implementation and calculation, but also avoids control limitations and heavy communication burden between DSP and FPGA. Besides, the proposed strategy effectively eliminates noise impact from sensors and increases accuracy. Simulation and experimental studies are implemented, and the results confirm the effectiveness of the proposed strategy. 1
Index terms-Capacitance monitoring, modular multilevel converters, reliability, PSC-PWM, submodule
I. INTRODUCTIONThe modular multilevel converter (MMC) has drawn considerable interests due to its advantages of modularity, scalability, high efficiency, low harmonic content and fault tolerance [1]- [3]. A multilevel voltage can be synthetized with the operation of the MMC and the SM switching frequency can be reduced without compromising the power quality [4]. Recently, the MMC is more attractive for renewable energy integration, medium-voltage motor drives, and electric railway supplies [5]- [7].The capacitor is one of the fragile components in the MMC [8]. Due to high energy density and low price [9], the