Open-ended system for high-level synthesis of flexible signal processors

Lanneer, D.; Catthoor, Francky; Goossens, Gert; Pauwels, Marc; Meerbergen, J. van; Man, H. De

doi:10.1109/edac.1990.136658

Cited by 20 publications

(5 citation statements)

References 11 publications

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“…Other HLS tools do not use such a feature. Nevertheless CALLAS (Biesenack et al 1993) and CATHEDRAL (Lanneer et al 1990) expect more information from the designer than just the pure behavioral description, to drive the synthesis process towards a specific target architecture. In HIS, the order of concurrent instructions is crucial.…”

Section: Resultsmentioning

confidence: 99%

“…For conditional instructions, CALLAS (Biesenack et al 1993) allows the user to choose the conditions to be hardwired, by direct specification of basic block boundaries. CATHEDRAL (Lanneer et al 1990) and GAUT (Martinet al 1990) remedy the second issue using directives included in the behavioral description that allow the designer to guide the m...s tool so precisely that it can generate the operative part prior to scheduling. To integrate the precise timing characteristics of the data-path into the scheduling, ALMA (Auge et al 1995, Brune11996) requires an explicit description of the data-path structure.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

User Guided High Level Synthesis

Augé

Bawa

Galle

et al. 1997

VLSI: Integrated Systems on Silicon

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This paper presents a High Level Synthesis (HLS) method for specialized coprocessors in embedded systems. In recent years, the synthesis of hardware systems has moved to a higher level of abstraction, but the existing tools leave very little initiative to the designer. With User Guided High Level Synthesis (UGH), we introduce the notion of Draft Data-Path Scheme (OOPS) which we consider an efficient way for the user to guide the HLS process. It describes the general structure of the datapath, without detailed information like signal-widths or physical implementation of multiplexers. Guided by these structural constraints, UGH intends to deliver a full data-path and a scheduled Finite State Machine that takes into account the detailed timing characteristics of the target physical library.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

User Guided High Level Synthesis

Augé

Bawa

Galle

et al. 1997

VLSI: Integrated Systems on Silicon

View full text Add to dashboard Cite

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“…Lanneer et al [222] developed in 1990 a design that was later adopted by Van Praet et al [326,327] in their implementation of CHESS, a well-known compiler targeting DSPs and application-specific instruction set processors (ASIPs).…”

Section: Chessmentioning

confidence: 99%

Instruction Selection

Blindell

2016

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“…For example, an addition of two 32 bit values could be performed on a 16 bit datapath with two additions (assuming an addition with carry is possible). This task employs the CATHEDRAL-2ND tool for expansion [28]. However, it relies heavily on our own operation library [29], which is two-fold: A machineindependent part describes constant folding and other peephole optimizations; a machine-dependent part describes all MEOs as well as the corresponding expansion rules.…”

Section: The General Approach: Macro Expansion and Chainingmentioning

confidence: 99%

“…By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. Because of the application-specific add-ons and the rather short lifetimes of a specific design, there is a need for retargetable software development tools, especially code-generators.…”

Section: Introductionmentioning

confidence: 99%

Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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Abstract. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. IntroductionIn the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. Because of the application-specific add-ons and the rather short lifetimes of a specific design, there is a need for retargetable software development tools, especially code-generators. OverviewIn the next section we will shortly discuss several related approaches to code generation and point out some differences of our system. Section 3 introduces the overall architecture and functionality of the CBC code generator. Section 4 explains the code selection task and the basic techniques used. In section 5 our algorithm is presented. We conclude the paper with experimental results. Points of major differences between our code selection approach and similar tasks in "classic" code generation (CG) are: -Complexity of datapaths. CBC has to deal with highly specialized and optimized datapaths. The hardware units make the efficient execution of frequently used operation sequences possible. Operation patterns for the functional units of these datapaths are much more complex than for standard microprocessors.-Type-handling. DSP algorithms may employ a large variety of different word lengths and numerical types. The hardware operators are restricted to fixed word lengths. A correct mapping must always be found. In most CG work this topic is neglected because language definitions (and hence the compilers) are restricted to "implementation-dependent" types. -Evaluation order. Approaches like [6,7] dealing with code selection assume a fixed evaluation order, which is usually derived from the imperative source code. There is no explicit scheduling phase included in the back-ends. Commonly, register allocation is performed during code selection. Most of the time this is done by graph coloring [4] or "on-the-fly".Parallelism of functional blocks. Most DSP architectures contain several functional units that work in parallel. Therefore, the final code cannot be emitted during or immediately after the code selection phase because partial instructions must be "compacted" into complete instructions at a later stage of compilation exploiting the possible para...

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Open-ended system for high-level synthesis of flexible signal processors

Cited by 20 publications

References 11 publications

User Guided High Level Synthesis

User Guided High Level Synthesis

Instruction Selection

Global code selection for directed acyclic graphs

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