OpenBox

Bremler-Barr, Anat; Harchol, Yotam; Hay, David

doi:10.1145/2934872.2934875

Cited by 147 publications

(35 citation statements)

References 20 publications

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“…In addition to the works discussed throughout the paper, the work on NFV performance acceleration can be classified into three categories: 1 relies on hardware accelerators to improve processing speed by offloading (part of) packet processing into an FPGA, GPU, or modern NIC [20,28,45,52,53,69,87,96,98,101,104,105]; 2 focuses on NFV execution models and tries to improve the performance of either the pipeline/parallelism model [43,55,61,86,103] or run-to-completion (RTC) model [37,76]; and 3 improves the performance of NFV by reducing/eliminating redundant operations and/or merging similar packet processing elements into (one) consolidated optimized equivalent [1,12,40,44,55,85]. The second category also includes efforts toward better scheduling & load balancing [4,5,7,41,50,94] or more efficient I/O [24,25].…”

Section: Related Workmentioning

confidence: 99%

PacketMill: toward per-Core 100-Gbps networking

Farshin

Barbette

Roozbeh

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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We present PacketMill, a system for optimizing software packet processing, which (i) introduces a new model to efficiently manage packet metadata and (ii) employs code-optimization techniques to better utilize commodity hardware. PacketMill grinds the whole packet processing stack, from the high-level network function configuration file to the low-level userspace network (specifically DPDK) drivers, to mitigate inefficiencies and produce a customized binary for a given network function. Our evaluation results show that PacketMill increases throughput (up to 36.4 Gbps ś 70%) & reduces latency (up to 101 µs ś 28%) and enables nontrivial packet processing (e.g., router) at ≈100 Gbps, when new packets arrive > 10× faster than main memory access times, while using only one processing core.

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Section: Related Workmentioning

confidence: 99%

PacketMill: toward per-Core 100-Gbps networking

Farshin

Barbette

Roozbeh

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…To the best of our knowledge, no existing work has explored this problem: specifically, merging two weighted DAGs into one while maximizing overlap. The most closely related works [8,43] provide suboptimal results, we elaborate on them in Section 9. Next, we more formally describe the problem.…”

Section: Merging Optimizationmentioning

confidence: 99%

“…The problem of merging two DAGs has been explored by several others [8,28,43]. At a high level, our work differs in two ways: first, we investigate a different formulation objective and second, we prove the complexity of the DAG merge problem and provide a more efficient heuristic based on simulated annealing.…”

Section: Dag-mergingmentioning

confidence: 99%

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P4Visor

Zheng

Benson

2018

Proceedings of the 14th International Conference on Emerging Networking EXperiments and Technologies

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Programmable data planes, PDPs, enable an unprecedented level of flexibility and have emerged as a promising alternative to existing data planes. Despite the rapid development and prototyping cycles that PDPs promote, the existing PDP ecosystem lacks appropriate abstractions and algorithms to support these rapid testing and deployment life-cycles. In this paper, we propose P4Visor, a lightweight virtualization abstraction that provides testing primitives as a first-order citizen of the PDP ecosystem. P4Visor can efficiently support multiple PDP programs through a combination of compiler optimizations and program analysis-based algorithms. P4Visor's algorithm improves over state-of-the-art techniques by significantly reducing the resource overheads associated with embedding numerous versions of a PDP program into hardware. To demonstrate the efficiency and viability of P4Visor, we implemented and evaluated P4Visor on both a software switch and an FPGA-based hardware switch using fourteen different PDP programs. Our results demonstrate that P4Visor introduces minimal overheads (less than 1%) and is one order of magnitude more efficient than existing PDPs primitives for concurrently supporting multiple programs. CCS CONCEPTS • Networks → Programmable networks; • Software and its engineering → Software testing and debugging;

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“…(1) a factor of 8 better efficiency, (2) almost 3x lower and predictable latency, and (3) 50% higher throughput than the OpenBox [16] data plane, a state of the art NFV system.…”

Section: Introductionmentioning

confidence: 99%

Metron

Katsikas

Barbette

Kostić

et al. 2020

ACM Trans. Comput. Syst.

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Deployment of 100Gigabit Ethernet (GbE) links challenges the packet processing limits of commodity hardware used for Network Functions Virtualization (NFV). Moreover, realizing chained network functions (i.e., service chains) necessitates the use of multiple CPU cores, or even multiple servers, to process packets from such high speed links. Our system Metron jointly exploits the underlying network and commodity servers’ resources: ( i ) to offload part of the packet processing logic to the network, ( ii ) by using smart tagging to setup and exploit the affinity of traffic classes, and ( iii ) by using tag-based hardware dispatching to carry out the remaining packet processing at the speed of the servers’ cores, with zero inter-core communication. Moreover, Metron transparently integrates, manages, and load balances proprietary “blackboxes” together with Metron service chains. Metron realizes stateful network functions at the speed of 100GbE network cards on a single server, while elastically and rapidly adapting to changing workload volumes. Our experiments demonstrate that Metron service chains can coexist with heterogeneous blackboxes, while still leveraging Metron’s accurate dispatching and load balancing. In summary, Metron has ( i ) 2.75–8× better efficiency, up to ( ii ) 4.7× lower latency, and ( iii ) 7.8× higher throughput than OpenBox, a state-of-the-art NFV system.

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OpenBox

Cited by 147 publications

References 20 publications

PacketMill: toward per-Core 100-Gbps networking

PacketMill: toward per-Core 100-Gbps networking

P4Visor

Metron

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