OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization

Waidyasooriya, Hasitha Muthumala; Hariyama, Masanori; Iwasaki, Hiromichi; Kobayashi, Daisuke; Omori, Yuya; Nakamura, Ken; Nitta, Koyo; Sano, Kimikazu

doi:10.1109/mwscas54063.2022.9859281

Cited by 2 publications

(1 citation statement)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, it is designed specifically for ultra-HD videos and targeted at high-performance computing applications. Waidyasooriya and Hariyama et al [7] presented an OpenCL-based FPGA-powered acceleration approach for H.266, wherein the transformation and quantization steps are implemented on FPGA to enhance performance. Notably, their experimental system employs high-end FPGA devices rather than edge computing platforms like our work.…”

Section: B Related Workmentioning

confidence: 99%

HLS and FPGA-Powered Streaming Video Encoder Accelerator for IoTs Edge Computing

Pham-Quoc

2024

JAIT

View full text Add to dashboard Cite

In recent years, Internet of Thing (IoT) applications with video processing deployed on edge computing platforms have been widely exploited for many areas, such as surveillance, object monitoring, or checkin/check-out systems. While H.264 video format is widely used for most modern cameras due to its efficiency, the computing power of edge computing platforms usually needs to be higher to process H.264 videos in acceptable intervals. This paper proposes an approach based on the high-level synthesis technique to accelerate video encoding by Field Programmable Gate Array (FPGA) platforms for edge computing applications. The H.264 encoding, chosen as our case study, is profiled to locate the computational-intensive functions to accelerate by FPGA. We use the high-level synthesis technique with optimization approaches, including loop unrolling, loop pipeline, function pipeline, and array partition, to generate the accelerator core. The core is then implemented with the hardware accelerator computing paradigm combining a host processor and the hardware accelerator cores for processing H.264 encoding. The approach is tested with an edge computing FPGA Ultra96-v2 board to validate the proposed approach and evaluate the performance. Experimental results show that we achieve speed-ups by up to 14.9 compared to an Advanced RISC Machine (ARM) quad-core processor. In terms of power consumption, our system requires 4.208 W.

show abstract

Section: B Related Workmentioning

confidence: 99%