Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors

Sáez, Juan Carlos; Fedorova, Alexandra; Prieto, Manuel; Vegas, Hugo

doi:10.1145/1787275.1787281

Cited by 29 publications

(51 citation statements)

References 14 publications

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“…The processor consists of two dies, and each die has six cores sharing a 6MB L3 cache. Each core has separate 64KB instruction and data L1 caches, and a 512KB pri- [6,10,14,15,16]. We configure cores into two core types, fast and slow cores which have 2.375:1 clock frequency ratio.…”

Section: Methodsmentioning

confidence: 99%

Virtualizing performance asymmetric multi-core systems

KwonYoungjin

KimChangdae

MaengSeungryoul

et al. 2011

SIGARCH Comput. Archit. News

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Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric multi-core systems, operating systems are responsible for scheduling threads to different types of cores. However, system virtualization poses a challenge for such asymmetric multi-cores, since virtualization hides the physical heterogeneity from guest operating systems. In this paper, we explore the design space of hypervisor schedulers for asymmetric multi-cores, which do not require asymmetry-awareness from guest operating systems. The proposed scheduler characterizes the efficiency of each virtual core, and map the virtual core to the most area-efficient physical core. In addition to the overall system throughput, we consider two important aspects of virtualizing asymmetric multi-cores: performance fairness among virtual machines and performance scalability for changing availability of fast and slow cores.We have implemented an asymmetry-aware scheduler in the open-source Xen hypervisor. Using applications with various characteristics, we evaluate how effectively the proposed scheduler can improve system throughput without asymmetry-aware operating systems. The modified scheduler improves the performance of the Xen credit scheduler by as much as 40% on a 12-core system with four fast and eight slow cores. The results show that even the VMs scheduled to slow cores have relatively low performance degradations, and the scheduler provides scalable performance with increasing fast core counts.

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Section: Methodsmentioning

confidence: 99%

Virtualizing performance asymmetric multi-core systems

KwonYoungjin

KimChangdae

MaengSeungryoul

et al. 2011

SIGARCH Comput. Archit. News

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“…The first type of schedulers, among which HASS is included, targeted efficiency specialization, by assigning the most CPU-intensive threads to fast cores [19,4]. The second type targeted TLP specialization, by assigning sequential applications and sequential phases of parallel applications to run on fast cores [25].…”

Section: Background and Related Workmentioning

confidence: 99%

“…TLP specialization was employed in our earlier algorithm called Parallelism-Aware (PA) [25] -this is the only such operating system algorithm of which we are aware. PA used the number of runnable threads as the approximation for the amount of parallelism in the application.…”

Section: Background and Related Workmentioning

confidence: 99%

Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems

Sáez

Shelepov

Fedorova

et al. 2011

Journal of Parallel and Distributed Computing

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“…The implementation of the algorithm and the experimental platform are described in more detail in a previous work. 10 In this experiment we use four fast and 12 slow cores. The applications used in Figure 3 are drawn from several benchmark suites, such as SPEC OpenMP 2001, PARSEC, MineBench, and NAS.…”

Section: Asymmetry-aware Schedulingmentioning

confidence: 99%

“…10 Using this waiting mode will further ensure that spinning threads do not waste the resources of fast cores. When making changes to the synchronization library is not an option, however, using adaptive synchronization mode will do the job.…”

Section: Asymmetry-aware Schedulingmentioning

confidence: 99%

Maximizing power efficiency with asymmetric multicore systems

et al. 2009

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and have different power characteristics. Using the same ISA on all cores means running the same binary on all cores without the need to compile code with a different compiler for each core type. This stands in contrast to heterogeneous-ISA systems, such as IBM's Cell or Intel's Larrabee, where the cores expose different ISAs, so the code must be compiled separately for each core type. Heterogeneous-ISA systems are not the focus of this article.A typical AMP consists of several fast and powerful cores (high clock frequency, complex out-of-order pipeline, and high power consumption) and a large number of slower low-power cores (low clock frequency, simple pipeline, and low power consumption). Complex and powerful cores are good for running single-threaded sequential applications because these applications cannot accelerate their performance by spreading the computation across multiple simple cores. Abundant simple cores, on the other hand, are good for running highly scalable parallel applications.Because of performance/power trade-offs between complex and simple cores, it turns out to be much more efficient to run a parallel application on a large number of simple cores than on a smaller number of complex cores that consume the same power or fit into the same area. In a similar vein, complex and powerful cores are good for running CPU-intensive applications that effectively use those processors' advanced microarchitectural features, such as out-of-order super-scalar pipelines, advanced branch prediction facilities, and replicated functional units. At the same time, simple and slow cores deliver a better trade-off between energy consumption and performance for memory-intensive applications that spend a majority of their execution time fetching data from off-chip memory and stalling the processor.A symmetric multicore processor (SMP) includes the cores of only one type: either the complex and powerful ones, as in the Intel Xeon or AMD Opteron processors, or the simple and in CoMPutinG SySteMS, a CPU is usually one of the largest consumers of energy. For this reason reducing CPU power consumption has been a hot topic in the past few years in both the academic community and the industry. In the quest to create more powerefficient CPUs, several researchers proposed an asymmetric multicore architecture that promises to save a significant amount of power while delivering similar performance as conventional symmetric multicore processors.An asymmetric multicore processor (AMP) consists of cores that use the same instruction set architecture (ISA) but deliver different performance

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Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors

Cited by 29 publications

References 14 publications

Virtualizing performance asymmetric multi-core systems

Virtualizing performance asymmetric multi-core systems

Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems

Maximizing power efficiency with asymmetric multicore systems

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