Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

Abstract

In this study, a novel multiple-gated (MG) thin-film transistor (TFT) with poly-Si nanowire (NW) channels is fabricated using a simple process flow. In the proposed new transistors, poly-Si NWs were formed in a self-aligned manner and were precisely positioned with respect to the source/drain, and the side-gate. Moreover, the NW channels are surrounded by three gates, i.e., top-gate, side-gate and bottom-gate, resulting in much stronger gate controllability over the NW channels, and greatly enhanced device performance over the conventional single-gated TFTs. Furthermore, the independently applied top-gate and/or bottom-gate biases could be utilized to adjust the threshold voltage of NW channels in a reliable manner, making the scheme suitable for practical applications.

Surface composition and interactions of mobile charges with immobilized molecules on polycrystalline silicon nanowires

“…Device structure and electrical characteristics of the poly-SiNW FET N-type poly-SiNW FETs fabricated using previously reported methods by us [1][2][3][4][5][6][7][21][22][23][24] were used as the nano-transducers in this study. The poly-SiNW was defined by a side-wall spacer technique [24] in a 6-inch Si wafer capped with a 100 nm SiO 2 layer and a 50 nm Si 3 N 4 layer.…”

“…An n-type field-effect transistor, comprising two poly-SiNWs that served as conducting channels and that had dimensions of 100 nm width and 1.6 m length, was fabricated using the sidewall spacer technique [4][5][6][7][21][22][23][24]. This technique is compatible with current commercial semiconductor process technologies and has been developed by our team, with an emphasis on applications in aqueous solutions [3][4][5][6][7][22][23][24][25].…”

Electric-Field Enhancement of a Gate-All-Around Nanowire Thin-Film Transistor Memory

“…There are, however, several critical issues relating to SOPs incorporating traditional TFT memory functions, such as low memory speeds and poor device properties, induced by grain-boundary trap states in channels and serious short-channel effects (SCEs) [6]. Recently, multiplegate devices that exhibit fully controlled surface potentials in their channel regions and suppressed SCEs have been prepared [7], [8]. Moreover, the additional electric field implies that more electrons tunnel into the storage layer over the channel, revealing that multiple-gate memory devices possess larger memory windows and superior programming/erasing (P/E) efficiencies.…”

Fabrication of CMOS-compatible Poly-Si Nanowire FET Sensor

“…Subsequently, a plasma treatment is employed after S/D activation. The NH 3 plasma treatment lasts 30 minutes which passiavtes the dangling bond of the PSNW buried channel interface [4]. This unique process improves the device stability in the aqueous solution environment.…”