OPMISR: the foundation for compressed ATPG vectors

Barnhart, C.; Brunkhorst, V.; Distler, F.; Farnsworth, O.; Keller, B.; Koenemann, B.

doi:10.1109/test.2001.966696

Cited by 296 publications

(106 citation statements)

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“…For a fault f with ndet (f) = 2, there are two or more options for transparent-scan sequences in T that detect it. Such a fault is likely to be detected by Tsel 1 . With a small number of faults that are not detected by Tsel 1 , Step 2 uses fault simulation with fault dropping to select additional sequences so as to detect all the faults in F Step 2 starts by assigning Tsel 2 = Tsel 1 .…”

Section: E Observabilitymentioning

confidence: 99%

“…For this purpose, recent and highly effective set covering algorithms are used. Compaction refers to a reduction in the test application timing, while at-speed testing points to the application of primary input sequences that contribute to the detection of delay defects [1]. The proposed procedure generates an initial test set that has a low test application time and consists of long sequences of primary input vectors applied consecutively, Experimental evidence suggests that the size of computed test sets can often be reduced by using set covering models and algorithms [14].…”

Section: Introductionmentioning

confidence: 99%

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Test Compaction of Logic Blocks by using Fault Identification Method

Vardhan¹,

Sathiskumar²

2015

International Journal of Advanced Research in Computer and Comm

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An arbitrary design implemented into a field-programmable gate array (FPGA). FPGA contains many logical blocks. Fault equivalence and fault dominance method are used to detect the fault with minimum time period. An approach provides transparent scan to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable. It uses n number of test configuration instead of 2 n number of test configuration by test code algorithm. Transparent scan enhances the ability to produce a compact test set for a group of logic blocks. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it chooses a subset that finds all the target faults, which are propagated by the complete set by using Modelsim and area is obtained by using the XILINX ISE 8.1 software.

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Section: E Observabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Test Compaction of Logic Blocks by using Fault Identification Method

Vardhan¹,

Sathiskumar²

2015

International Journal of Advanced Research in Computer and Comm

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“…This is another source of UMA, as explained in the following example. This problem could be easily solved by using the repeat fill feature of some ATEs and adding special "scan op-codes" to account for the repeat [30]. However, if the number of repeats is not considerable, then adding the extra scan op-codes does not provide a viable solution [30], as it increases the memory requirements instead of reducing them.…”

Section: Motivation and Contributionsmentioning

confidence: 99%

Addressing useless test data in core-based system-on-a-chip test

Gonciari

Al-Hashimi

Nicolici³

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Methods to reduce test application time include generation of compact tests [1,2] and the use of multiple scan chains [3]. Methods to reduce tester storage requirements include methods to reduce test input data volume [4][5][6][7][8][9][10][11] and methods to reduce test response data volume [3,6,[12][13][14][15][16][17]. Some of these methods [6,13,14,16,17] address unknown values in the output response of the circuit.…”

Section: Introductionmentioning

confidence: 99%

“…Test response data compaction can be achieved using combinational compactors (also called space compactors) [12] and/or sequential compactors [13], which are typically multiple input signature registers and are also called time compactors. Time compactors have infinite impulse response property.…”

Section: Introductionmentioning

confidence: 99%