Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications

Chau, R.; Datta, Suman; Majumdar, Amlan

doi:10.1109/csics.2005.1531740

Cited by 108 publications

(59 citation statements)

References 52 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[10][11][12] InAs has been used in a number of NW devices (see the literature for examples [13][14][15][16] ), and is one of the most promising materials for high-speed electronics [17] due to its high electron mobility, high electron saturation velocity, and low resistance contacts; still, it has proven difficult to combine InAs directly with Si. At the same time there is a strong drive from the electronics industry to integrate high-performance nanomaterials with Si [1] using methods compatible with existing Si processing. Contamination from the commonly used Au particles in the vapor-liquid-solid (VLS) mechanism [18] for NW growth is a concern because Au is an impurity in Si, which traps electrons and holes by deep-level recombination centers.…”

mentioning

confidence: 99%

“…A successful combination of these two material systems would add new functionality and increased performance compared to standard Si technology. [1] Although these advantages have long been recognized, the monolithic integration of devicequality III-V materials on Si remains a major challenge. In this work, we report on heteroepitaxial growth of InAs nanowires (NWs) directly on Si substrates by employing self-assembled organic coatings to create an oxide template that guides NW nucleation.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Epitaxial Growth of Indium Arsenide Nanowires on Silicon Using Nucleation Templates Formed by Self‐Assembled Organic Coatings

et al. 2007

View full text Add to dashboard Cite

The material properties of III-V semiconductors are in many ways superior to those of Si. Examples of these properties are the possibilities for high electron mobilities and the direct bandgap in most III-V semiconductors. Even so, Si remains the standard material in the electronics industry. A successful combination of these two material systems would add new functionality and increased performance compared to standard Si technology.[1] Although these advantages have long been recognized, the monolithic integration of devicequality III-V materials on Si remains a major challenge. In this work, we report on heteroepitaxial growth of InAs nanowires (NWs) directly on Si substrates by employing self-assembled organic coatings to create an oxide template that guides NW nucleation. Such a template resembles the growth masks used in selective-area epitaxy of nanostructures on III-V substrates. [2][3][4] Importantly, Au, which is commonly used for NW synthesis but not compatible with modern complementary metal oxide semiconductor (CMOS) processing, is avoided. The described nucleation method presents clear advantages in terms of epitaxial quality and control of NW size and density distributions compared to previous results achieved on Si using catalyst-free NW growth. The control demonstrated in the fields of self-assembled [5] and printed organic nanostructures [6,7] illustrates how the method may be extended to more complex patterning in future work. NWs have been the subject of much study and have great potential as a future technology platform. [8,9] One unique feature of the NW geometry is the small NW/substrate interface, which could provide a path to monolithic integration of highperformance materials, such as heterostructure III-V device structures, onto the mainstream Si platform. The small interface helps to mitigate antiphase domain formation, and accommodates a considerable mismatch in lattice constants (ca. 12 % for InAs on Si) and thermal expansion coefficients. [10][11][12] InAs has been used in a number of NW devices (see the literature for examples [13][14][15][16] ), and is one of the most promising materials for high-speed electronics [17] due to its high electron mobility, high electron saturation velocity, and low resistance contacts; still, it has proven difficult to combine InAs directly with Si. At the same time there is a strong drive from the electronics industry to integrate high-performance nanomaterials with Si [1] using methods compatible with existing Si processing. Contamination from the commonly used Au particles in the vapor-liquid-solid (VLS) mechanism [18] for NW growth is a concern because Au is an impurity in Si, which traps electrons and holes by deep-level recombination centers. [19] Inevitably, some traces of Au will contaminate process equipment or end up in the nanostructures grown. [20,21] For this reason, Au is not compatible with modern CMOS processing. NW growth without foreign metal catalyst particles thus offers an attractive alternative to the VLS method. Approaches such...

show abstract

mentioning

confidence: 99%

mentioning

confidence: 99%

Epitaxial Growth of Indium Arsenide Nanowires on Silicon Using Nucleation Templates Formed by Self‐Assembled Organic Coatings

et al. 2007

View full text Add to dashboard Cite

show abstract

“…However, current Si-based complimentary metal-oxide-semiconductor (CMOS) technology is nearing the physical limits of its scaling potential, and with the end in sight of the traditional technology roadmap [1], only a radical departure from Si-based technologies can ensure continued technological progress [2]. New material innovations [3][4][5], novel device architectures [6][7][8][9], heterogeneous technology co-integration [10], new functionalities [11], and their monolithic integration onto Si are projected to continue transistor miniaturization beyond the Si CMOS era. Moreover, interconnect bottlenecks for both inter-chip and intra-chip communication are projected to be major impediments to energy-efficient performance scaling.…”

Section: Introductionmentioning

confidence: 99%

Heterogeneously grown tunable group-IV laser on silicon

et al. 2016

View full text Add to dashboard Cite

Tunable tensile-strained germanium (epsilon-Ge) thin films on GaAs and heterogeneously integrated on silicon (Si) have been demonstrated using graded III-V buffer architectures grown by molecular beam epitaxy (MBE). epsilon-Ge epilayers with tunable strain from 0% to 1.95% on GaAs and 0% to 1.11% on Si were realized utilizing MBE. The detailed structural, morphological, band alignment and optical properties of these highly tensile-strained Ge materials were characterized to establish a pathway for wavelength-tunable laser emission from 1.55 μm to 2.1 μm. High-resolution X-ray analysis confirmed pseudomorphic epsilon-Ge epitaxy in which the amount of strain varied linearly as a function of indium alloy composition in the InxGa1-xAs buffer. Cross-sectional transmission electron microscopic analysis demonstrated a sharp heterointerface between the epsilon-Ge and the InxGa1-xAs layer and confirmed the strain state of the epsilon-Ge epilayer. Lowtemperature micro-photoluminescence measurements confirmed both direct and indirect bandgap radiative recombination between the Γ and L valleys of Ge to the light-hole valence band, with L-lh bandgaps of 0.68 eV and 0.65 eV demonstrated for the 0.82% and 1.11% epsilon-Ge on Si, respectively. The highly epsilon-Ge exhibited a direct bandgap, and wavelength-tunable emission was observed for all samples on both GaAs and Si. Successful heterogeneous integration of tunable epsilon-Ge quantum wells on Si paves the way for the implementation of monolithic heterogeneous devices on Si

show abstract

“…In order to achieve such characteristic features in a real time operation scenario it will be a hard tenacious task [11] . More in the present modern world the electronic device must have low response time along with low power consumption provided the cost of the device must be in a nominal range [7] . Using a conventional MOSFET device can no longer sustain such a modern day challenge.…”

Section: …………………………………………………………………………………………………… Introduction:-mentioning

confidence: 99%