Opportunities for RTL and gate level simulation using GPUs

Zhang, Yanqing; Ren, Haoxing; Khailany, Brucek

doi:10.1145/3400302.3415773

Cited by 11 publications

(2 citation statements)

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“…Zhang [43] called for a renewal in GPU-accelerated RTL simulation research by leveraging recent advances in GPU-compute APIs designed for machine learning.…”

Section: Parallel Rtl Simulationmentioning

confidence: 99%

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

Emami¹,

Kashani²,

Kamahori³

et al. 2023

Preprint

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The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware heavily uses cycle-accurate simulation of register-transfer-level (RTL) designs. The best software RTL simulators can simulate designs at 1-1000 kHz, i.e., more than three orders of magnitude slower than hardware. Faster simulation can increase productivity by speeding design iterations and permitting more exhaustive exploration.One possibility is to use parallelism as RTL exposes considerable fine-grain concurrency. However, state-of-the-art RTL simulators generally perform best when single-threaded since modern processors cannot effectively exploit fine-grain parallelism.This work presents Manticore: a parallel computer designed to accelerate RTL simulation. Manticore uses a static bulk-synchronous parallel (BSP) execution model to eliminate runtime synchronization barriers among many simple processors. Manticore relies entirely on its compiler to schedule resources and communication. Because RTL code is practically free of long divergent execution paths, static scheduling is feasible. Communication and synchronization no longer incur runtime overhead, enabling efficient fine-grain parallelism. Moreover, static scheduling dramatically simplifies the physical implementation, significantly increasing the potential parallelism on a chip. Our 225-core FPGA prototype running at 475 MHz outperforms a state-of-the-art RTL simulator on an Intel Xeon processor running at ≈ 3.3 GHz by up to 27.9× (geomean 5.3×) in nine Verilog benchmarks.

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“…Zhang [43] called for a renewal in GPU-accelerated RTL simulation research by leveraging recent advances in GPU-compute APIs designed for machine learning.…”

Section: Parallel Rtl Simulationmentioning

confidence: 99%

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

Emami¹,

Kashani²,

Kamahori³

et al. 2023

Preprint

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“…EDA tools typically involve solving large-scale optimization problems with heavy numerical computation, especially at the physical design stage, and extensive work is devoted to accelerating these solvers with modern parallel computing hardware like multicore CPUs or GPUs [26,29,98]. Many recent studies have explored GPU's opportunity in EDA problems [59,91,167,168]. Still, developing good GPU implementation of EDA algorithms is challenging.…”

Section: Acceleration With Deep Learning Enginementioning

confidence: 99%

Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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With the down-scaling of CMOS technology, the design complexity of very large-scale integrated (VLSI) is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 90s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interests in incorporating ML to solve EDA tasks. In this paper, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

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