Opposition Harmony Search algorithm based optimal sizing of CMOS analog amplifier circuit

Maji, K. B.; Jaiswal, Harshita; Kar, Rajib; Mandal, Durbadal; Ghoshal, Sakti Prasad

doi:10.1109/ticst.2015.7369375

Cited by 2 publications

(3 citation statements)

References 13 publications

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“…In the paper proposed by Azam et al, (2016) [7], a methodology for simultaneous optimization was formulated for CMOS logic gates for power-and-noise margin and energy-and-noise-margin. The sizing parameter for functionality improvement of various gates had been extended to satisfy other figures of merit, such as dependability, power, and energy.…”

Section: Work Proposed Bymentioning

confidence: 99%

“…Opposition Dependent Harmony Search technique (OHS) was utilized in the research by Maji et al, (2015) [7] for the formulation of Differential Amplifier with CMOS Transistor in an optimum manner. With the help of rules such as memory rule, a pitch fine-tuning rule, and an initialization procedure, every answer in Harmony Memory (HM) produced provides the best outcome with the smallest possible error fitness in ndimensional exploration spaces.…”

Section: Work Proposed Bymentioning

confidence: 99%

“…The value of the Aspect ratio for fifth transistor S 5 is computed from the least input voltage. The value of V DS5 (sat) and S 5 is calculated subsequently as shown in (6) and (7). The value of S 6 is calculated by making the second pole (p2) equivalent to the product of 2.2 * Gain Bandwidth Product and making an assumption by which = as shown in (8) and (9).…”

Section: * = (5)mentioning

confidence: 99%

See 2 more Smart Citations

Design Optimization of Power and Area of Two-Stage CMOS Operational Amplifier Utilizing Chaos Grey Wolf Technique

Maddileti¹,

Govindarajulu²,

Sivappagari³

2020

IJACSA

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Low Power Dissipation is an emerging challenge in the current electronics industry. Area shrinking has found the most prominent place and is the foundation of every constricted size in the utilization of CMOS circuits in Integrated Circuit Manufacturing. Functionality in terms of rapidity, dissipation of power, etc. are strongly influenced by the dimensions of transistors in many CMOS Integrated Circuits. The significant formulation parameters in CMOS circuit design to perform optimization of the above-mentioned parameters, and various techniques were projected earlier to a maximum extent possible. Latency, Power, and Dimension are significant parameters in the design of CMOS based IC design. Most analog circuit reduction in terms of size as parameter typically describes solitary or many objectives-controlled optimization issues. The eminent challenges with regards to size and power dissipation can be described as problems that are typically encountered under certain conditions. In this study, the design of a two-stage CMOS Differential Amplifier applying the nature-inspired Grey Wolf Algorithm for optimizing the area and power is utilized. To enhance the formulation terms concerning important considerations such as the amount incurred, strength, and functionality; a computerized formulation approach is used. This formulated design proposal will meet specifications such as positive and negative Slew Rate, Unity Gain Bandwidth and Phase Margin, etc. Chaos theory can be induced into the Grey Wolf Optimization Algorithm (CGWO) with the help of speeding global convergence metric i.e. Speed. The results obtained from CGWO are then analyzed with the functionality of other prevailing optimization techniques employed in the analog circuit sizing. Depending on the investigations, CGWO functions reduce the dimensions of the circuit and analyze the prevailing techniques by achieving a healthier rate of convergence and power dissipation with low value.

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Section: Work Proposed Bymentioning

confidence: 99%

Section: Work Proposed Bymentioning

confidence: 99%