Optical interconnection networks for high-performance systems

Cheng, Qixiang; Glick, Madeleine; Bergman, Keren

doi:10.1016/b978-0-12-816502-7.00020-8

Cited by 13 publications

(4 citation statements)

References 137 publications

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“…In particular, 2018 marks the beginning of a new era that saw the advent of a drastic architectural change of supercomputers: Summit replaced Sunway TaihuLight as the #1 supercomputer and hence, GPUs displaced manycore CPUs. At that moment, the year-to-year performance has increased by 60%, but the byte-to-flop ratio, measuring the communication performance, has decreased as much as 8× [1].…”

Section: A Communication-to-computation Ratiomentioning

confidence: 99%

Implications of Reduced Communication Precision in a Collocated Discontinuous Galerkin Finite Element Framework

Rogowski

Dalcín

Parsani

et al. 2021

2021 IEEE High Performance Extreme Computing Conference (HPEC)

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Compute capability of high-performance hardware has been growing at immense rates, increasing over 130x in the last decade. Communication bandwidth, however, only grew by a factor of 6x in the same time, leading to a significant decrease in the byte-to-flop metric. This trend leads us to the situation where, in many cases, computation is virtually free, and the dominant cost of a parallel application comes from its communication cost. We expect this trend to continue and, hence, the parallel application wall-clock time to be increasingly correlated with the amount of data transferred between the nodes involved. In order to alleviate this communication bottleneck, we test several communication-reducing schemes based on the idea of using higher precision for the inner cells and lower precision communication. For every approach, we report the resulting network traffic and weigh it against the decreased accuracy. We perform our experiments in a collocated Discontinuous Galerkin finite element method framework (DG-FEM) applied in Computational Fluid Dynamics (CFD). First, we present a parametric study using the method of manufactured solutions on a 3D compressible Navier-Stokes supersonic cube. Using this method allows us to quantify communication reducing schemes' impact on the error in test cases representing a range of solution polynomial degrees and problem sizes. Finally, we verify the findings on a full-scale CFD problem, flow around the delta wing, and report on methods' consistency as the number of processes and the number of halo elements change.

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Section: A Communication-to-computation Ratiomentioning

confidence: 99%

Implications of Reduced Communication Precision in a Collocated Discontinuous Galerkin Finite Element Framework

Rogowski

Dalcín

Parsani

et al. 2021

2021 IEEE High Performance Extreme Computing Conference (HPEC)

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“…Underlying interconnection network plays a key role in scaling the DCs to guarantee performance of traffic-boosting applications [2]. Therefore, it is of crucial importance to design an interconnection network which is highly scalable, power consumption and cost efficient.…”

Section: Introductionmentioning

confidence: 99%

HFOS$$_L$$: hyper scale fast optical switch-based data center network with L-level sub-network

et al. 2022

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“…This fact allows the possibility of carrying out complex operations and algorithms but brings more challenges. The resulting growth of High-Performance Computing (HPC) systems, supercomputers and data centers are increasingly reshaping the network infrastructure and the interconnection network [3], which on the other hand increased the energy consumption and cost budgets [4]. In recent years, Networks-on-Chips (NoCs) have been proposed as a methodology for simplifying and improving the design of Multiprocessor Systems-on-Chips (MPSoC) [5], [6] and [7], 3D architectures [8], routing and mapping algorithms have been proposed [9], [10], [11] and [12], Several reconfigurable ONoCs have been presented [13], [14], [15] and [16] so far.…”

Section: Introductionmentioning

confidence: 99%

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

et al. 2021

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Photonic networks and software-defined networks are two promising technologies to improve network-onchips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the 8x8 network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.

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Optical interconnection networks for high-performance systems

Cited by 13 publications

References 137 publications

Implications of Reduced Communication Precision in a Collocated Discontinuous Galerkin Finite Element Framework

Implications of Reduced Communication Precision in a Collocated Discontinuous Galerkin Finite Element Framework

HFOS$$_L$$: hyper scale fast optical switch-based data center network with L-level sub-network

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

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