Optimal Allocation of TCSC and DG Unit for Congestion Management in Deregulated Power Systems

Abstract

In this paper, minimization of total harmonic distortion (THD) is discussed for the output voltage of multilevel inverter. THD minimization is an efficient method in reduction of the harmonic components of the inverter's output voltage. In multilevel inverters, the switching angles can be selected in a way that the output voltage THD will be minimized. Given that THD minimization is an optimization problem, intelligent algorithm is found to be an appropriate alternative in this regard. Shuffled Frog Leaping Algorithm and Harmony Search Algorithm are employed to find optimum switching angles to generate desired voltage value in the possible minimum THD. The obtained results of two algorithms are compared with each other to determine that which algorithm is more efficient in this regard. Also, both simulation and experimental results indicate superiority of this approach over the published work using GA in this concept. The experiments are conducted on a seven-level inverter to validate the feasibility of presented approach. IntroductionIn the recent years, power electronics engineers have centralized their attention to multilevel inverters. Compared to conventional two level inverters, stepwise output voltage is the basic advantage of multilevel inverters. This advantage will have some results such as better Electromagnetic Capability (EMC), lower switching losses, higher power quality, reduction of dv/dt stresses, lower total harmonic distortion (THD), needlessness of a transformer at distribution voltage and lower rating on power semiconductor switches [1][2][3][4][5]. Due to the advantages mentioned above for multilevel inverters, they are employed in many applications such as: distributed generation [6], micro grids [7][8], FACTs devices [9], High Voltage Direct Current (HVDC) [10], and electrical vehicles [11][12]. Multilevel inverters are mainly classified into three configurations which are the flying capacitor [13], diode clamped [14][15] and cascaded multilevel inverters [16]. Multilevel inverters are divided into two categories from the aspect of DC source value, which are called symmetric and asymmetric topologies. For DC voltage sources, capacitors, batteries and renewable energy sources can be implemented. In symmetric topology all DC sources have the same value but in asymmetric topology they have different values. Asymmetric multilevel inverters generate higher number of voltage steps for a definite number of switches compared to symmetric ones. The stepwise output voltage of multilevel inverters composed by a number of DC voltage sources [17]. An increase in the number of steps, will lead to generation of a near sinusoidal output voltage of multilevel inverter. This results in a considerable reduction in output voltage THD. Nevertheless, problems such as voltage unbalance, circuit layout and voltage clamping, limit the possible number of levels. Consequently, reducing the THD of output voltage waveform is a vital issue in designing useful and efficient multilevel inverters. Hence, impro...