Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

Abstract

In this work, we study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a fourterminal switch controlled by a Boolean literal. These types of arrays are commonly called as switching lattices. We propose optimal and heuristic algorithms that minimize lattice sizes to implement a given Boolean function. The algorithms are mainly constructed on a technique that finds Boolean functions of lattices having independent inputs. This technique works recursively by using transition matrices representing columns and rows of the lattice. It performs symbolic manipulation of Boolean literals as opposed to using truth tables that allows us to successfully find Boolean functions having up to 81 variables corresponding to a 9×9-lattice. With a Boolean function of a certain sized lattice, we check if a given function can be implemented with this lattice size by defining the problem as a satisfiability problem. This process is repeated until a desired solution is found. Additionally, we fix the previously proposed algorithm that is claimed to be optimal. The fixed version guarantees optimal sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed algorithms by considering lattice sizes and runtimes in comparison with the recently proposed three algorithms.

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

“…In this section, we present the results of JANUS, MEDEA, and the methods of [15], [16], [19]. Note that JANUS and MEDEA, developed in Perl, use espresso [28] as a logic minimization tool to find the ISOP forms of logic functions and their duals, glucose4.1 [29] to solve a SAT problem, and SCIP2.1 [30] to solve a 0-1 ILP problem.…”

“…The proposed algorithms can be found at https://github.com/leventaksoy/Lattices. We used the updated version of the exact method of [15] where an issue, that may cause the method to miss some paths in a switching lattice, was fixed [19]. The results of the method [16] were obtained using a developed tool that can find the lattice realizations of sub-functions decomposed by the algorithm of [31] and can merge these realizations into a single lattice.…”

“…In [18], the target function is synthesized with multiple lattices sharing the common ones, but adding extra logic gates which may not be desirable due to the wires between these gates and lattice control inputs. The method of [19] determines a number of promising lattice candidates and uses a method of [15] to find if one of these lattices leads to a solution.…”

“…Thus, a solution with a δ × (2v − 1) lattice is found where δ is the degree of the target function. In the dual product separation (DPS) method [19], the u products of the dual of target function are placed on the rows of a lattice separated by a row full of ones, filling the unspecified entries of the lattice with constant 0. Thus, a solution with a (2u − 1) × γ lattice is found where γ is the degree of the dual of target function.…”

“…This is mainly because the excessive area due to the placement and routing of transistors and gates [14] does not occur in the design of a switching lattice and the realization of a logic function using a lattice generally needs less number of switches than that in the conventional CMOS realization as shown in Fig 2. In recent years, many algorithms have been introduced to realize a logic function on a switching lattice using the fewest number of switches [15], [16], [17], [18], [19], [20]. However, while the exact algorithm [15] can only handle relatively small instances, the approximate algorithms [16], [17], [18], [19] can find solutions that are far away from the minimum. Hence, in this article, we present the approximate algorithm of [20], called JANUS, that can find better solutions using less computational effort when compared to the existing approximate algorithms.…”