Optimal assignment of high threshold voltage for synthesizing dual threshold CMOS circuits

Tripathi, Neeraj; Bhosle, A.; Samanta, Debasis; Pal, Ajit

doi:10.1109/icvd.2001.902665

Cited by 24 publications

(24 citation statements)

References 7 publications

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“…Algorithm 1 is very similar to the previous one in Ref. 16. Every edge in the circuit graph has a weight in order to decide which gate should be changed.…”

mentioning

confidence: 95%

“…The algorithm to a subgraph is similar to the gate-level algorithm presented in Ref. 16 which can assign more high-threshold gates on the noncritical path than the algorithm presented in Ref. 14.…”

Section: Algorithm 1: Forward Depth-first Low-v T Assignmentmentioning

confidence: 99%

“…In this way, the transistors within a vertex that are driven by the same logic signal will be assigned to the same threshold. The assignment of threshold voltages to the transistors in the circuit can be represented as assigning a threshold voltage to a vertex v ∈ V , [14][15][16] or assigning a threshold voltage to an edge. 17 Thus, this allows treating the dual-V t optimization problem as a kind of graph problem.…”

Section: Signal-path Circuit Modelmentioning

confidence: 99%

“…However, the drawback in Ref. 16 that one has to reiterate the whole circuit every time one gate changes still remains in these two algorithms. Algorithm 3 brings an improved version of Algorithm 2.…”

mentioning

confidence: 99%

“…16, a different idea is presented which initialized the circuit by assigning a high threshold voltage to all the gates of the circuit, i.e., it essentially configures the circuit to give the minimum power. The algorithm selects a gate which is on the critical path and then assigns V T Hlow to it.…”

mentioning

confidence: 99%

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SIGNAL-PATH-LEVEL DUAL-V_t ASSIGNMENT FOR LEAKAGE POWER REDUCTION

Wang

Yang

Wang

2006

J CIRCUIT SYST COMP

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Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage highperformance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signalpath-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

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“…Algorithm 1 is very similar to the previous one in Ref. 16. Every edge in the circuit graph has a weight in order to decide which gate should be changed.…”

mentioning

confidence: 95%

Section: Algorithm 1: Forward Depth-first Low-v T Assignmentmentioning

confidence: 99%

Section: Signal-path Circuit Modelmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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SIGNAL-PATH-LEVEL DUAL-V_t ASSIGNMENT FOR LEAKAGE POWER REDUCTION

Wang

Yang

Wang

2006

J CIRCUIT SYST COMP

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Optimal dual-V/sub T/ assignment for low-voltage energy-constrained CMOS circuits

Samanta¹,

Pal²

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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In this paper we have addressed the problem of realizing dual-V T CMOS circuits for battery-operated hand held and portable systems. As the battery life is of primary concern, an algorithm is proposed to realize circuits with near minimal energy requirement in the standby mode as well as in the active mode, at the expense of some performance. An efficient algorithm for dual-V T assignment has been developed, which assigns high-V T to larger number of transistors compared to the existing approaches, leading to higher reduction in power. Experiments have been carried out to study the reduction in power requirement with the increase in delay (with corresponding increase in low-V T ) compared to the highest performance single-V T realization. Our algorithm has been tested using standard ISCAS benchmark circuits. Experimental results have established that, by compromising small performance (5 to 10% increase in delay), it is possible to realize CMOS circuits using dual-V T technology with near-minimal energy requirement.

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