Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis

Fiege, Nicolai; Sittel, Patrick; Zipf, Peter

doi:10.1109/fpl57034.2022.00047

2022 32nd International Conference on Field-Programmable Logic and Applications (FPL) 2022

DOI: 10.1109/fpl57034.2022.00047

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Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis

Nicolai Fiege

Patrick Sittel

Peter Zipf

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Cited by 2 publications

References 34 publications

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BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

Fiege

Zipf

2023

ACM Trans. Reconfigurable Technol. Syst.

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Modulo scheduling is the premier technique for throughput maximization of loops in high-level synthesis by interleaving consecutive loop iterations. The number of clock cycles between data insertions is called initiation interval (II). For throughput maximization, this value should be as low as possible; therefore its minimization is the main optimization goal. Despite its long historical existence, modulo scheduling always remained a relevant research topic over the last years with many exact and heuristic algorithms available in literature. Nevertheless, we are able to leverage the scalability of modern Boolean Satisfiability (SAT) solvers to outperform state-of-the-art ILP-based algorithms for latency-optimal modulo scheduling for both integer and rational IIs. Our algorithm is able to compute valid modulo schedules for the whole CHStone and MachSuite benchmark suites, with 99% of the solutions being proven to be throughput-optimal for a timeout of only 10 min per candidate II. For various time limits, not a single tested scheduler from the state-of-the-art is able to compute more verified optimal solutions or even a single schedule with a higher throughput than our proposed approach. Using an HLS toolflow we show that our algorithm can be effectively used to generate Pareto-optimal FPGA implementations regarding throughput and resource usage.

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BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

Fiege

Zipf

2023

ACM Trans. Reconfigurable Technol. Syst.

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Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design

Fiege,

Zipf

2024

ACM Trans. Reconfigurable Technol. Syst.

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The end of Moore’s law and Dennard scaling emphasizes the need for application-specific computing architectures to achieve high resource and energy efficiency and real-time performance. The concept of a silicon compiler remains an enduring aspiration for design time reduction. In order to generate hardware implementations at register transfer level from behavioral descriptions, design automation tools must address challenging and interdependent problems, including allocation, scheduling, and binding. Additionally, manual intervention by the user is necessary to balance the resources vs. performance trade-off via, for example, function inlining or loop unrolling/pipelining. Existing approaches typically solve these problems sequentially, compromising optimality in favor of simplicity and run-time. Here we show how to model the whole model-based design flow as one holistic integer linear programming (ILP) formulation aiming at consistently deriving the optimal microarchitecture for any given application. Incorporating clock gating minimizes the number of useless operations with negligible resource overhead (if any), while always guaranteeing optimal throughput. The unified nature of the proposed ILP model enables implementations unmatched by state-of-the-art approaches in terms of resource efficiency and measured power consumption. These results facilitate a streamlined design flow for highly optimized embedded systems in the context of model-based design.

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Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis

Cited by 2 publications

References 34 publications

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design

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