Optimal bus sizing in migration of processor design

Abstract

The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimally-tuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sum-of-delays problem. An iterative algorithm to find the optimally-tuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed.

On optimal ordering of signals in parallel wire bundles

“…For a fixed order of wires, the problem of allocating widths and spaces to maximize performance in tuning of bus structures was proposed in [3] and solved in [25]. The wire sizing problem has been addressed in [4] and [5] for a single net.…”

“…Signal delays are expressed by an Elmore model using simple approximations for wire capacitances and wire resistance. The delay of signal i σ is given in [25] by…”

Interconnect Bundle Sizing Under Discrete Design Rules

“…Several interconnect resizing algorithms were proposed to increase clock frequency [2] [3], to reduce dynamic power [4], and to maintain some tradeoff between both [5]. Most of prior work on interconnect resizing for power and delay reduction [2]- [5] assumed that interconnect width and spacing can vary in a continuous range allowed by design rules.…”

The complexity of VLSI power-delay optimization by interconnect resizing

“…Unfortunately, power and speed are often in conflict with each other and their tradeoff is delicate and challenging. As a part of the VLSI design optimization techniques, interconnects are subject to small adjustments for setting their widths and spaces [4] [5].…”