Optimal cascade lumped model of deep submicron on-chip interconnect with distributed parameters

Ma, Qilong; Yang, Yintang; Li, Yuejin; Xinzhang, Jia

doi:10.1016/j.mee.2004.11.011

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…The implementation of different functions in electronic boards necessitates complex structures interconnections. As reported in [2][3][4][5][6], the latter can be a source of signal degradations. For example, to ensure the synchronisation of the digital data [7], the signal integrity (SI) plays important roles.…”

Section: State Of the Art On The Interconnect Propagation Delaymentioning

confidence: 87%

Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

Ravelo

Eudes

2011

Int J Numerical Modelling

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SUMMARY This article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high‐speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.

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Section: State Of the Art On The Interconnect Propagation Delaymentioning

confidence: 87%

Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

Ravelo

Eudes

2011

Int J Numerical Modelling

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“…An innovative design method must be especially developed the digital PCB tree clock. Therefore, optimal methods of modelling [5] and simulation [6] are necessary.…”

Section: Introductionmentioning

confidence: 99%

Novel Tee-Shaped Topology Theory of Low- and High-Pass NGD Double-Type Function

Jia

Wan

Frnda³

et al. 2022

IEEE Access

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Recent investigation reports that certain electronic circuits operate with the unfamiliar negative group delay (NGD) function. It is fundamentally stated that the NGD circuits can be classified in different types. For example, we have the simplest ones as LP and HP NGD circuit types. So far, all the NGD studies are focused on simple type function. In step up of the research about the NGD electronic circuit engineering, this paper develops an original theory of electronic circuit topology operating with double NGDtype behavior. The study consists in the theorization of three-port circuit simultaneously generating LP and HP NGD function types. The proposed three-port innovative circuit under study is innovatively composed of resistive-capacitive (RC) network of Tee-shaped topology. Moreover, the LP and HP double-NGD circuit is a first order cell which does not contain any inductive component. The LP and HP NGD analyses of the Tee-topology is based on the 3-D S-matrix modelling. Analytical investigation based on classical circuit theory is elaborated to determine the S-matrix model from the equivalent admittance matrix. The identification of the double-NGD function is established from the LP-and HP-NGD canonical forms. Hence, the specific double-NGD characteristics are defined in function of the R and C elements constituting the three-port topology. To validate the developed double-NGD theory, a proof-of-concept (PoC) of SMD lumped component-based three-port circuit is designed, simulated, fabricated and tested. The calculated, simulated and measured results from the three-port circuit PoC prototype in very good agreement confirm the double-NGD behavior. The proposed innovative NGD three-port circuit design is useful in the future for the synchronization of signals propagating through multi-way communication system.INDEX TERMS Negative group delay (NGD), low-pass (LP) NGD function, high-pass (HP) NGD function, RC-network, circuit theory, three-port topology, LP-HP double-NGD analysis.

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“…Moreover, methods enabling the improvement of the performance optimization were also proposed [19,20]. Until now, most of the existing methods have been based on first-order [10,21,22] or second-order [23][24][25][26][27] polynomial approximations of the interconnection transfer functions.…”

Section: Introductionmentioning

confidence: 99%

Microelectronic interconnect modeling with a periodical lumped RLC-network

Ravelo¹

2013

Turkish Journal of Electrical Engineering and Computer Sciences

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Optimal cascade lumped model of deep submicron on-chip interconnect with distributed parameters

Cited by 6 publications

References 9 publications

Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

Novel Tee-Shaped Topology Theory of Low- and High-Pass NGD Double-Type Function

Microelectronic interconnect modeling with a periodical lumped RLC-network

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