2005
DOI: 10.1002/ett.1035
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Optimal design of an all-digital chip timing recovery loop for direct-sequence spread-spectrum systems

Abstract: SUMMARYNoncoherent digital delay lock loops (DDLL) are suited for chip timing synchronisation in band-limited direct-sequence spread-spectrum (DSSS) demodulators. The diffusion approximation and the singular perturbation method are used in this paper to calculate the mean time to lose lock (MTLL) of the DDLL. Loop bandwidth optimisation for first order loop with severe Doppler is presented. A simple design rule for the loop bandwidth and a systematic approach for the loop threshold calculation are presented.

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Cited by 3 publications
(3 citation statements)
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“…which coincides with the more complicated derivation on the basis of the loop transfer function in [1][2][3][4][5][5][6][7]. The square root of the stationary variance in Equation (16) yields the jitter RMS value.…”
Section: Analytical Solution Of the First-order Sde-jitter Rms Value supporting
confidence: 69%
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“…which coincides with the more complicated derivation on the basis of the loop transfer function in [1][2][3][4][5][5][6][7]. The square root of the stationary variance in Equation (16) yields the jitter RMS value.…”
Section: Analytical Solution Of the First-order Sde-jitter Rms Value supporting
confidence: 69%
“…The crucial jitter results follow from the simple OU random processes without the integral evaluation that the conventional jitter computation [1][2][3][4][5][5][6][7] requires. We obtain for the second-order Langevin DLL the identical jitter and total loop bandwidth as for the first-order DLL in Section 2, which is due to the identical channel delay functions T .t/ in Equation (4) corresponding to a constant velocity v 0 .…”
Section: Analytical Solution Of the First-order Sde System-jitter Rmsmentioning
confidence: 99%
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