Optimal Design of Reconfigurable Arbiter Algorithm used in On-Chip S.O.C.

Abstract

This paper presents reconfigurable arbiter is placed in arbitration to the enhancement of the data transfer and reduce delay, latency and bandwidth b/w master core and slave cores. It provides high performance in real-time application on-chip S.O.C. The performance of arbitration in individual process was the earlier stages of the arbitration technique. In the processing of arbitration technique in a single step-by-step process the transfer of data from one multiple master to multiple core's causes delays. The simulations were done using XILINX 14.5.