Optimal fault-tolerant design approach for VLSI array processors

Mapping multiple algorithms into a reconfigurable systolic array

“…Two factors that determine the performance of a systolic array are the total number of PEs and the total computation time. Studies in [4] [9] found that these two factors depend only on the transformation matrix and the length of the loop. The results are showed below.…”

“…Definition 1 [4]: The number of PEs, n p , is the number of different elements in the set {(x, y)}, which can be computed by the following theorem. Theorem 1 [4]: The number of PEs is l 1 l 2 l 3 if |a j | ≥ l j for some j = 1, 2, 3, and…”

“…Many systolic array designs have been reported in the past several decades and some are equipped with fault tolerance [2][3][4][5][6]. However, all these designs are algorithm-based, which -----------------978-1-4244-1643-1/08/$25 c 2008 IEEE means one design is for solving one problem.…”

“…Although the design in [8] could compute multiple problem instances, that design only works for problems with the same data dependency. Previous studies [4] developed a systematic approach to mapping one algorithm into a systolic array with fault tolerance, and the fault tolerance is achieved by time/space redundancy. Actually, the redundant version of the same algorithm instances for fault tolerance could be replaced by some new algorithm instances.…”

“…Actually, the redundant version of the same algorithm instances for fault tolerance could be replaced by some new algorithm instances. In this paper, we propose a reconfigurable systolic array architecture for mapping multiple problems into a single reconfigurable systolic array according to the space-time mapping approach [4,7]. The mapping procedure is based on a linear transformation of index space and data dependency.…”