Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming

Abstract

{ System level design and behavior transformations have been rapidly establishing themselves as design steps with the most inuential impact onnal performance metrics, throughput and latency, o f a design. In this paper we develop a formal ILPbased approach for throughput and latency optimization when algorithm-architecture matching, retiming, and pipelining are considered simultaneously. The effectiveness of the approach is demonstrated on several real-life examples.

Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retiming

“…We derived a new proof, using a transformation from the equal-subset problem which shows that throughput (latency) optimization using algorithm selection is an NPcomplete problem, even when only algorithms with no delays are considered [5]. The new proof is also more general in the sense that it covers variants of the problem when pipelining is used in conjunction with retiming and the target is latency optimization instead of throughput maximization.…”

“…The present mathematical model can be easily extended to handle synchronous data-ow computations with computation blocks having time non-equidistant inputs and more than one output (Case II) by applying a set of substitutions discussed in the technical report of this paper [5].…”

“…Each block in Figure 1 can be implemented using a variety of algorithms (CDFGs) and architectures; e.g. commonly used DCT algorithms include Lee's, Wang's, planar rotation, DIF (decimation in frequency), DIT (decimation in time) and FFTbased algorithms [5]. The architecture choices include various DSP, video, microcontroller, and microprocessor chips from many v endors.…”

“…We also pose the optimization problem at the graph level of abstraction. Figure 1 shows the CDFG of the transform domain adaptive LMS lter [5]. Sigma denotes vector sum, DCT is the direct discrete cosine transform.…”

Fast algorithms for retiming large digital circuits

“…Other Applications Retiming has been used during the technology mapping step in FPGA synthesis [15,16,91,129,133], to improve circuit partitioning [66], for scheduling in high level synthesis [12,132] and in multiprocessor scheduling [11]. Other approaches for retiming for system level throughput optimization include [89,134]. Retiming has been combined with other logic synthesis techniques in [4,63,65,80,81,90,99].…”