Optimal Integration Process for Elimination of Abnormal Striation on Wafer Dual Damascene Processes

Abstract

This paper is focused on optimal lithography processes using copper back-end-of-line (BEOL) semiconductor wafer integration technology and a solution to the problem of defect reduction on a semiconductor wafer. The pattern collapse observed in this process and numerous defects were prevented by optimizing the process module tuning. A novel semiconductor process on various pattern designs and deep pattern aspect ratio effects of a submicron semiconductor structure were included in this study. In addition to the experimental wafer manufacturing process, the electrical device data and defect reduction checking were also included.