Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation

Craig, Kyle; Shakhsheer, Yousef; Calhoun, Benton H.

doi:10.1145/2333660.2333714

Cited by 6 publications

(10 citation statements)

References 8 publications

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“…The body of these PMOS switches is tied to the virtualto avoid forward body bias, which results in a significant increase in the leakage current through these switches when the 1 st and/or the 2 nd switches are activated [7]. The gate drive signals of the 3 rd and 4 th PMOS switches are either connected to the ground when they are activated or to if they are inactivated.…”

Section: Structure Support For Fine-grained Ultra Dynamic Voltage Scamentioning

confidence: 99%

“…We may replace some PMOS switches by NMOS switches and reduce area overhead while maintaining the same performance and power consumption, as illustrated in [7]. The 1 st and 2 nd PMOS switches cannot be replaced by NMOS ones.…”

Section: Type Of Header Power Switchesmentioning

confidence: 99%

“…Adjustable DC-DC converters tend to have limited efficiency over broad output voltage ranges, and they take hundreds of micro-seconds to switch between different supply levels especially in the nearthreshold regime [6]. An alternative implementation approach called local voltage dithering (LVD) uses header power switches to connect circuit blocks to one of the several power supply rails, thereby allowing for faster switching [7] [8]. The LVD approach supports application of fine-grained ultra DVS (UDVS) down to the near-threshold regime and to smaller internal circuit blocks.…”

Section: Introductionmentioning

confidence: 99%

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Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Wang

Lin

Pedram

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation. Digital circuits supporting such burst-mode applications should work in both the near-threshold regime and the super-threshold regime for brief time periods. This work proposes the structure support of fine-grained ultra dynamic voltage scaling (UDVS) from the traditional strong-inversion region to the near-threshold region, with limitations on the number of power rails. The number, type, and size of the power switches are jointly optimized to minimize the overall energy consumption of the UDVS circuit block, meanwhile satisfying the target delay or frequency requirement at each DVS level. The proposed optimization framework properly accounts for the dynamic energy consumption as well as the leakage energy consumption through all the power switches during both the operation time and stand-by time of the circuit block. Experimental results on 22nm Predictive Technology Model demonstrate the effectiveness of the proposed optimization framework.

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Section: Structure Support For Fine-grained Ultra Dynamic Voltage Scamentioning

confidence: 99%

Section: Type Of Header Power Switchesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Wang

Lin

Pedram

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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“…In addition, though subV T circuits do now draw large amount of currents to cause significant IR drop directly from the supply, our architecture ( Figure 2.3) compels that PDVS headers will be used to incorporate power-gating and DVS capabilities. With PDVS header design, it can be expected to have a worst case -10% degradation in the virtual rail supply voltage [27]. Thus, a characterization at -10% supply voltage degradation should be done.…”

Section: Modifications During Cell Characterizationmentioning

confidence: 99%

Synthesis Based Design Techniques for Robust, Energy Efficient Subthreshold Circuits

Zhang

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Energy efficiency is increasingly becoming the main concern for many emerging system-onchip (SoC) applications such as wireless sensor networks (WSNs), body area sensor nodes (BSNs), or portable electronics, which require ultra low power and high energy efficiency. In state-of-the-art situations where the SoC is powered from ambient harvested energy instead of a battery, the constraint of high energy efficiency is put to the extreme in order for the SoC to sustain its operation. Though supply voltage scaling down to near-(NV T ) and subthreshold(subV T ), which we refer to together as ultra low voltages (ULVs), has provided drastic quadratic savings in dynamic energy, design of circuits at ULVs still poses important challenges.One of those critical issues is robust design. From a system perspective, for batteryless BSNs that rely on energy harvesting, robust design means maximizing energy efficiency so that the power consumed is less than that harvested, thus ensuring robust, sustained operation of the SoC.Robust design of digital circuits means coping with the acute effects of process variations at ULVs, which are a cause of huge concern. Brute force or conventional methods used in superthreshold to ensure robustness may compromise the goal of energy efficiency at ultra low voltages, or may no longer be sufficient to ensure robustness in this design region. This thesis looks at design techniques to ensure robust design at ultra low voltages, as well as techniques that lower the energy overhead while ensuring a robust design.ii For the digital circuits involved in SoCs, ULV operation entails exponentially slower speeds, which not only mean a limit on the throughput available, but also an increase in the significance of leakage current, which may undermine our purpose of energy efficiency. Thus, for SoC architecture, judicious considerations as to the size, amount, type, and communication of modules with respect to energy efficiency must be studied to ensure a deployable design. In this work, we investigate the energy efficiency vs. module platform flexibility design space to answer the question of which type of platform (general purpose processor, FPGA, or ASIC) is most energy efficient in being the main driving force behind digital processing. The exploration of design space also leads to the resulting architecture of a taped-out batteryless BSN SoC.Increased sensitivity to process variation makes robust timing closure a key challenge at ULVs, and thus it is exceptionally hard for industry to accept ULV designs as future solutions.From a synthesis flow standpoint, this challenge translates to extreme difficulty in timing closure.Straightforward methods to decrease variation and meet timing such as device upsizing are not well suited at ULVs because they compromise the end goal of ultra low power. Conventional methodologies during timing closure that estimate the amount of variation apparent, such as setting a flat timing derate (a value by which all cell delays are multiplied to simulate the effects of ...

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“…Limited energy is available with the intelligent sensor nodes. Suppression of energy consumption is therefore the primary concern in the design of intelligent sensor nodes [131] - [141], [279] - [285]. Alternatively, performance is typically not a critical issue in these self-sustaining applications.…”

Section: Power/ground Gating In Ultra Low Power / Ultra Low Voltage Imentioning

confidence: 99%

Noise mitigation in low leakage MTCMOS circuits

Jiao¹

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It is the journey, not the arrival, that matters." When I am approaching the ending point of the journey of my Ph. D. study, I would like to thank all the people who help me along the way.I would like to thank my supervisor, Professor Volkan Kursun, for his tireless guidance and continuous support during my Ph. D. study. His dedication and hard working stimulates me to devote more time into my research work. His strictness on every step of my study helps to maintain the high quality of my academic publications. He is unswervingly pursuing perfection, inspiring me to refine myself continuously. He spends tremendous amount of time in helping me to develop the necessary skills to be a successful and independent researcher. I will always remember his motivation to be an outstanding scientist. I also would like to thank Professor Zilong Wen, Professor Chi-Ying Tsui, Professor Jie Yuan, Professor Pedro V. Sander, and Professor Eby G. Friedman for serving on my Ph. D. thesis defense committee. My special thanks go to Professor Eby G. Friedman for coming all the way from the U. S. to attend my final oral examination. I am also grateful to Professor Amine Bermak for his service in my Ph. D. thesis proposal. I appreciate the support from all my colleagues and friends. I would like to thank Hong Zhu, Yanan Sun, Shairfe M. Salahuddin, and Khawar Sarfraz of Nanoelectronic Circuits and Gigascale Systems Lab for the help in the past years. I am also very grateful to the staff members, Siu Fai Luk, Kenny Pang, and Iris Ting, at the Department of Electronic andComputer Engineering for their constant support. Furthermore, I would like to express my thanks to Zhenyu Wu, Dongge Tang, and Guangcai Ding for the long term inspiration. I also would like to thank Xuan Li for the constant encouragements. There are too many friends who I would like to thank in Hong Kong, mainland China, the U. S., and Europe. The friendships will be imprinted in my mind forever. This dissertation is made possible with the support and encouragement from my parents. I am deeply indebted to my parents for their endless love. They are always with me whenever I vii am frustrated by my tough work. I would like to share every moment of joy of my life with them in the future. They will also be proud of my success in my future career. This dissertation is the ending of one journey, but the beginning of a new journey. All the helps, encouragements, and love that I received during my Ph. D. study will become my motivation to achieve more in the future.

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Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation

Cited by 6 publications

References 8 publications

Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Synthesis Based Design Techniques for Robust, Energy Efficient Subthreshold Circuits

Noise mitigation in low leakage MTCMOS circuits

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