Optimal regulation of traffic flows in networks-on-chip

Jafari, Fahimeh; Lu, Zhonghai; Jantsch, Axel; Yaghmaee, Mohammad Hossein

doi:10.1109/date.2010.5457070

Cited by 12 publications

(7 citation statements)

References 4 publications

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“…Thus, for an arbitrary injected traffic load, traffic regulators may be needed to make sure that the amount of injected traffic in a specified period does not exceed a specified level. In [55] a buffer optimization problem is solved under worst case performance constraints based on network calculus. In [56], Bakhouya et al also present a model based on network calculus to estimate the maximum end-to-end and buffer size for mesh networks; the delay bounds calculated for the flows are not hard bounds and real values may be larger.…”

Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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Abstract-Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches.

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Section: Related Workmentioning

confidence: 99%

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Rahmati

Murali

Benini³

et al. 2013

IEEE Trans. Comput.

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“…Weighted round-robin policy is also assumed in Jafari et al (2010). It considers a NoC where in each port, the number of virtual channels is not less than the number of flows, and that VCs are served with a per-packet round-robin policy.…”

Section: Network On Chipmentioning

confidence: 99%

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

Boyer

Graillat

Dinechin

et al. 2020

Performance Evaluation

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The Kalray MPPA2-256 processor integrates 256 processing cores and 32 management cores on a chip. Theses cores are grouped into clusters and clusters are connected by a high-performance network on chip (NoC). This NoC provides hardware mechanisms (ingress traffic limiters) that can be configured to offer service guarantees.This paper introduces a network calculus formulation, designed to configure the NoC traffic limiters, that also computes guarantee upper bounds on the NoC traversal latencies. This network calculus formulation accounts for the traffic shaping performed by the NoC links, and can be solved using linear programming. This paper then shows how existing network calculus approaches (the Separated Flow Analysis -SFA ; the Total Flow Analysis -TFA ; the Linear Programming approach -LP) can be adapted to analyze this NoC. The delay bounds obtained by the four approaches are then compared on two case studies: a small configuration coming from a previous study, and a realistic configuration with 128 or 256 flows.From theses cases studies, it appears that modeling the shaping introduced by NoC links is of major importance to get accurate bounds. And when all packets have the same size, modeling it reduces the bound by 20%-25% on average.

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“…Jafari et al [7] propose a flow regulation to reduce the delay and backlog bounds in SoC. A prediction-based flow control is presented by Ogras and Marculescu [11], it predicts the cases of possible congestion in the network, and controls the packet injection rate at the sources of the traffic in order to regulate the total number of packets in the NoC.…”

Section: Related Workmentioning

confidence: 99%

Eeep

Hassan

Pétrot

Locatelli

et al. 2011

Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip

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MPSoC platforms face an increasing diversity of traffic requirements due to the interaction between cores. This interaction is driven by the applications run by the user, and leads to the coexistence of the best effort traffic and the guaranteed service traffic in the same platform. We propose Extreme End-to-End Protocol (EEEP) as a new end-to-end flow control protocol to access SDRAMs through a multiport memory controller in NoC-based MPSoCs. Our protocol considers the memory access within a system approach. It exploits the occupancy rate of the requests queue in the memory controller within the policy of the traffic injection at the master Network Interfaces (NIs) level. By controlling the best-effort traffic shape, EEEP improves the bandwidth and the latency of the guaranteed service traffic.

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Optimal regulation of traffic flows in networks-on-chip

Cited by 12 publications

References 4 publications

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

Eeep

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