Optimal Scaling Methodologies and Transistor Performance

Skotnicki, T.; Bœuf, F.

doi:10.1007/3-540-26462-0_6

Cited by 9 publications

(4 citation statements)

References 12 publications

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“…to decrease the gate insulator thickness T ox proportionally to the decrease of the channel length. For an optimized FET structure, a rule of thumb suggests T ox =L ch $ 1=30 [19]. The device platform for modern microelectronics is known as MOSFET.…”

Section: A Electronic Switch (Fet)mentioning

confidence: 99%

Science and Engineering Beyond Moore's Law

2012

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Section: A Electronic Switch (Fet)mentioning

confidence: 99%

Science and Engineering Beyond Moore's Law

2012

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“…( 1), because the intrinsic saturation drain current is a function of gate voltage. The saturation drain current I Dsat0 per unit channel width when R S ¼ R D ¼ 0 Ám is used as 27,28)…”

Section: Analytical Saturation Drain Current Modelmentioning

confidence: 99%

Structural Dependence of Source-and-Drain Series Resistance on Saturation Drain Current for Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

Yoon

Hiroki

Kobayashi

2013

Jpn. J. Appl. Phys.

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The structural dependence of series-resistance effects on the saturation current is investigated in sub-20 nm metal–oxide–semiconductor field-effect transistors (MOSFETs). For planer bulk, silicon-on-insulator (SOI), and multi gate (MG) MOSFETs, the reduction rate of the saturation current is calculated using an analytical current model in high-performance (HP), low-operating-power (LOP), and low-standby-power (LSTP) technologies. In HP technology, the reduction rates are 29.0, 25.3, and 22.1% for bulk, SOI, and MG MOSFETs, respectively. In LOP technology, the reduction rates are 23.8, 21.5, and 20.7% for bulk, SOI, and MG MOSFETs, respectively. In LSTP technology, the reduction rates are about 17% for all devices. In HP technology, the ratio of the series resistance to the channel resistance is the dominant factor for the reduction rate. In LOP technology, the ratio of the over drive voltage to the supply voltage is the dominant factor. In LSTP technology, both the resistance and voltage ratios are the dominant factors.

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“…Therefore, internal voltages (V 0 GS ; V 0 DS ) are given by [25][26][27] V 0 where R S and R D are the source and drain resistances per unit gate width, respectively. When the intrinsic MOSFET operates in the saturation region, the drain current equation is used as follows: 28,29)…”

Section: Analytical Saturation Drain Current Modelmentioning

confidence: 99%

Higher-Order Effect of Source–Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

Yoon¹,

Hiroki²,

Kobayashi³

2012

Jpn. J. Appl. Phys.

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The saturation drain current including a higher-order effect of series resistance is investigated in sub-20 nm metal-oxide-semiconductor fieldeffect transistors (MOSFETs). The reduction in current by the resistance is calculated using a derived analytical current model. As a result, the reduction rate increases from 15.8 to 24.0% as the gate length decreases from 32 to 18 nm. Ratios of the Nth-order term to the sum of all absolute order terms are calculated. As the gate length decreases, the effect of higher-order terms becomes important for analyzing the effect of the series resistance. Normalized expansion components of the higher-order resistance-effect are compared with the reduction rate to determine the physical reasons for the reduction increase. We find that the ratio of the source resistance to the channel resistance is the dominant factor in device design and development for sub-20 nm MOSFETs.

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Optimal Scaling Methodologies and Transistor Performance

Cited by 9 publications

References 12 publications

Science and Engineering Beyond Moore's Law

Science and Engineering Beyond Moore's Law

Structural Dependence of Source-and-Drain Series Resistance on Saturation Drain Current for Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

Higher-Order Effect of Source–Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

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