Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Sivakumar

International Journal of Electrical Engineering & Education

2020

The 3D integrated circuits are enlarging the technology with lots of potentials which establish vertical interconnection between different dies or layers. In 3D-integrated circuit fabrication, congestion, and wirelength minimization are challenging processes. To overcome these problems, we proposed a novel optimization approach for useful partitioning, placement, and routing. Our proposed work consists of four significant stages, including partitioning, placement, routing, and fault diagnosis in through silicon via and spare through silicon via allocation. Firstly, the QuadTree partitioning method executed by the partitioning process. QuadTree method partitions the layer into four subdivisions and remains until it finds no space for partitioning. AND logic is proposed to overcome the congestion problem during placement. In the second stage, the functioning of the hybrid particle swarm optimization and simulated annealing algorithm proposed by the placement process. Particle swarm optimization computes fitness function for six constraints, specifically wirelength, area, power, cross talk, temperature, and delay. The simulated annealing places circuits in the specified area with the computed fitness function. In every 45°, Kruskal’s based octi-linear Steiner tree algorithm that establishes routes performs the routing by the third stage. In the last stage, fault detection in through silicon via and spare through silicon via allocation processes are executed using the support vector machine algorithm and dedicated switch. Support vector machine classifies the TSV into two, which includes regular and redundant through silicon via. The spare through silicon via allocation performed by using a dedicated switch. Finally, the proposed work evaluated based on metrics such as wire length, area, temperature, delay, and run time.

Section: Introductionmentioning

confidence: 99%

RETRACTED: A novel optimization approach for partitioning-based place and route in 3D integrated circuits

Sivakumar

International Journal of Electrical Engineering & Education

2020

2014 International Conference on Computational Intelligence and Communication Networks

“…An efficient process for solving hard optimization problems is the modified Genetic Algorithm (MGA). By using the simulated evolution process of GA, the partitioning solutions retain better characteristics of earlier populations [4]. This inherent parallel nature of GA provides it with an advantage over other approaches which uses one single solution.…”

Section: ) Area and Number Of Partitionsmentioning

confidence: 99%

An Efficient Approach to VLSI Circuit Partitioning Using Evolutionary Algorithms

Sangwan

Verma

Kumar

2014

Circuit Partitioning generally formulated as graph partitioning problem is an important step in physical design of circuits. The use of Evolutionary techniques is increasingly used to solve NP complete problems i.e. applications for logic minimization and simulation heuristics. This paper explores the evolutionary approach of genetic algorithm and propose a hybrid technique involving the strengths of the existing techniques resulting in a better partitioning and placement of circuits. It can further be extended to the Hardware/Software boundary of algorithms and can be applied to real world physical design problems.

“…[25] and [26] explore the advantage of evolutionary algorithms aimed at reducing the delay and area in partitioning and floorplanning. In turn, this would reduce the wirelength.…”

Section: Related Workmentioning

confidence: 99%

Complexity issues in some clustering problems in combinatorial circuits

Donovan¹,

Mkrtchyan²,

Subramani³

2014

Preprint

The modern integrated circuit is one of the most complex products that has been engineered to-date. It continues to grow in complexity as the years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface [21]. The process of mapping an electronic design to a chip involves a number of physical design stages, one of which is clustering. In this paper, we focus on problems in clustering which are critical for more sustainable chips. The clustering problem in combinatorial circuits alone is a source of multiple models. In particular, we consider the problem of clustering combinatorial circuits for delay minimization, when logic replication is not allowed (CN). The problem of delay minimization when logic replication is allowed (CA) has been well studied, and is known to be solvable in polynomial-time [16]. However, unbounded logic replication can be quite expensive. Thus, CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for these problems.