Optimal spilling for CISC machines with few registers

Appel, Andrew W.; George, Lal

doi:10.1145/378795.378854

Cited by 97 publications

(61 citation statements)

References 16 publications

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“…The technique is included in register allocators such as [8]. Originally, rematerialization aims to avoid spill loads by recomputing the loaded value thus saving the memory access.…”

Section: Aggressive Rematerializationmentioning

confidence: 99%

“…Overview of Register Allocator. We implemented our aggressive rematerialization in the register allocator proposed by Appel et al in [8]. Register allocation is performed in two phases in [8].…”

Section: Figure 3 Rematerialization With Multiplementioning

confidence: 99%

“…Thus, we attempt to adopt current register allocation algorithms to perform CCSM allocation. In particular, we choose to modify the register allocation algorithm proposed in [8] since it achieves optimal spilling.…”

Section: Compiler Controlled Secure Memorymentioning

confidence: 99%

“…To extend the algorithm in [8] for data not registerallocable, we need to compute the live range for it properly. During the following discussion, we assume pointer analysis has been done and we have certain points-to information for each memory reference.…”

Section: Compiler Controlled Secure Memorymentioning

confidence: 99%

“…After identifying all resident candidates for the CCSM and their live ranges, we can adopt the optimal spilling algorithm in [8] to perform the actual allocation. The allocation problem can still be solved by integer linear programming (ILP) efficiently.…”

Section: Compiler Controlled Secure Memorymentioning

confidence: 99%

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Compiler Optimizations to Reduce Security Overhead

Zhang

Zhuang

Pande

International Symposium on Code Generation and Optimization (CGO'06)

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In this work, we present several compiler optimizations to reduce the overhead due to software protection. We first propose an aggressive rematerialization algorithm which attempts to maximally realize non-trusted values from other trusted values thereby avoiding the security cost for those non-trusted values. We further propose a compiler technique to utilize the secure storage in our machine model efficiently. To optimize the security cost on data that has to be stored in non-trusted storage, we propose a data grouping technique. Security operations can be performed over the group of data instead of over each piece separately. We show an interesting application of the data grouping technique to reduce the security cost.We test the effectiveness of our optimizations on a recently proposed software protection scheme that involves large overhead. Our results show that the above optimizations are effective and reduce the security overhead significantly.

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“…The technique is included in register allocators such as [8]. Originally, rematerialization aims to avoid spill loads by recomputing the loaded value thus saving the memory access.…”

Section: Aggressive Rematerializationmentioning

confidence: 99%

Section: Figure 3 Rematerialization With Multiplementioning

confidence: 99%

Section: Compiler Controlled Secure Memorymentioning

confidence: 99%

Section: Compiler Controlled Secure Memorymentioning

confidence: 99%

Section: Compiler Controlled Secure Memorymentioning

confidence: 99%

See 3 more Smart Citations

Compiler Optimizations to Reduce Security Overhead

Zhang

Zhuang

Pande

International Symposium on Code Generation and Optimization (CGO'06)

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Optimal integrated code generation for VLIW architectures

Keßler

Bednarski

2006

Concurrency and Computation

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SUMMARYWe present a dynamic programming method for optimal integrated code generation for basic blocks that minimizes execution time. It can be applied to single-issue pipelined processors, in-order-issue superscalar processors, VLIW architectures with a single homogeneous register set, and clustered VLIW architectures with multiple register sets. For the case of a single register set, our method simultaneously copes with instruction selection, instruction scheduling, and register allocation. For clustered VLIW architectures, we also integrate the optimal partitioning of instructions, allocation of registers for temporary variables, and scheduling of data transfer operations between clusters. Our method is implemented in the prototype of a retargetable code generation framework for digital signal processors (DSPs), called OPTIMIST. We present results for the processors ARM9E, TI C62x, and a single-cluster variant of C62x. Our results show that the method can produce optimal solutions for small and (in the case of a single register set) medium-sized problem instances with a reasonable amount of time and space. For larger problem instances, our method can be seamlessly changed into a heuristic.

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Register allocation and spilling using the expected distance heuristic

Burroughs

2016

Softw Pract Exp

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Summary The primary goal of the register allocation phase in a compiler is to minimize register spills to memory. Spill decisions by the allocator are often made based on the costs of spilling a virtual register and, therefore, on an assumed placement of spill instructions. However, because most allocators make these decisions incrementally, placement opportunities can change as allocation proceeds, calling into question the basis for the original spill decision. An alternative heuristic to placement costs for spill decisions focuses on where program execution will lead. Spilling the virtual register with the Furthest Next Use is known to lead to the minimum number of loads under certain conditions in straight‐line code. While it has been implemented in register allocation in different forms, none of these implementations fully exploits profiling information. We present a register allocator that can adapt to improved profiling information, using branch probabilities to compute an Expected Distance to Next Use for making spill decisions and block frequency information to optimize post‐allocation spill instruction placement. Spill placement is optimized after allocation using a novel method for minimizing spill instruction costs on the control flow graph. Our evaluation of the allocator compared with LLVM recognizes more than 36% and 50% reductions, on average, in the number of dynamically executed store and load instructions, respectively, when using statically derived profiling information. When using dynamically gathered profiling, these improvements increase to 50% and 60% reductions, on average, for stores and loads, respectively. Copyright © 2016 John Wiley & Sons, Ltd.

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Optimal spilling for CISC machines with few registers

Cited by 97 publications

References 16 publications

Compiler Optimizations to Reduce Security Overhead

Compiler Optimizations to Reduce Security Overhead

Optimal integrated code generation for VLIW architectures

Register allocation and spilling using the expected distance heuristic

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