Optimal static WCET-aware scratchpad allocation of program code

Falk, Heiko; Kleinsorge, Jan C.

doi:10.1145/1629911.1630101

Cited by 71 publications

(42 citation statements)

References 10 publications

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“…An effective scratchpad configuration is obtained by storing the N most frequently used memory blocks, where N is the maximum number of memory blocks that the scratchpad can hold. With execution traces, identifying the most frequently used memory blocks is nearly trivial; however, in general more sophisticated optimization techniques have to be used (Falk and Kleinsorge 2009).…”

Section: Static Scratchpadsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Section: Static Scratchpadsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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“…Cache locking are also shown to be quite effective for improving average-case execution time [13]. Finally, optimal on-chip scratchpad memory allocation to improve the WCET has been explored in [5,18].…”

Section: Related Workmentioning

confidence: 99%

WCET-centric partial instruction cache locking

Ding

Liang

Mitra

2012

Proceedings of the 49th Annual Design Automation Conference

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Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in Worst-case Execution Time (WCET) estimation due to unpredictable access latencies. Modern embedded processors often include cache locking mechanism for better timing predictability. As the cache contents are statically known, memory access latencies are predictable leading to precise WCET estimates. Moreover, by carefully selecting the memory blocks to be locked, WCET estimate can be reduced compared to cache modeling without locking. Existing static instruction cache locking techniques strive to lock the entire cache to minimize the WCET. We observe that such aggressive locking mechanisms may have negative impact on the overall WCET as some memory blocks with predictable access behavior get excluded from the cache. We introduce a partial cache locking mechanism that has the flexibility to lock only a fraction of the cache. We judiciously select the memory blocks for locking through accurate cache modeling that determines the impact of the decision on the program WCET. Our synergistic cache modeling and locking mechanism achieves up to 68% reduction in WCET for a large number of embedded benchmark applications.

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“…Scratchpad allocation for reducing worst case execution time of sequential programs has been addressed in (e.g., [8,9]) and most recently in [10]. However, concurrent applications require to consider task dependency and multiprocessssor architectures require the modeling of shared resources.…”

Section: Related Workmentioning

confidence: 99%

Static bus schedule aware scratchpad allocation in multiprocessors

Chattopadhyay

Roychoudhury

2012

SIGPLAN Not.

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Compiler controlled memories or scratchpad memories offer more predictable program execution times than cache memories. Scratchpad memories are often employed in multi-processor system-onchip (MPSoC) platforms which seek to meet the performance needs of embedded applications while limiting power consumption and timing unpredictability. Scratchpad allocation schemes optimize performance while ensuring predictable execution times (as compared to caches).In this work, we develop a compile-time scratchpad allocation framework for multi-processor platforms, where the processors (virtually) share on-chip scratchpad space and external memory is accessed through a shared bus. Our allocation method considers the waiting time for bus access while deciding which memory blocks to load into the shared scratchpad memory space. Incorporating the bus schedule into our scratchpad allocation method leads to a global optimization of an application, as compared to employing local scratchpad allocation schemes in individual processors which locally optimize the per-processor execution time. We evaluate the efficacy, sensitivity and efficiency of our memory allocation scheme on two real-world embedded applications -an application controlling an Unmanned Aerial Vehicle (UAV), and a (fragment of) an in-orbit spacecraft software.

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Optimal static WCET-aware scratchpad allocation of program code

Cited by 71 publications

References 10 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

WCET-centric partial instruction cache locking

Static bus schedule aware scratchpad allocation in multiprocessors

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