Optimal Superblock Scheduling Using Enumeration

Shobaki, Ghassan; Wilken, Kent

doi:10.1109/micro.2004.27

Cited by 23 publications

(26 citation statements)

References 19 publications

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“…The basic block instruction scheduling problem is to find a minimum length schedule for a basic block-a straight-line sequence of code A.M. Malik · T. Russell · M. Chase · P. van Beek ( ) School of Computer Science, University of Waterloo, Waterloo, Canada e-mail: vanbeek@uwaterloo.ca with a single entry point and a single exit point-subject to precedence, latency, and resource constraints. 1 Basic block scheduling is important in its own right and also as a building block for scheduling larger groups of instructions such as superblocks (Cooper and Torczon 2004;Shobaki and Wilken 2004).…”

Section: Introductionmentioning

confidence: 99%

Learning heuristics for basic block instruction scheduling

et al. 2007

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Instruction scheduling is an important step for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction scheduling is to find a minimum length schedule for a basic block-a straightline sequence of code with a single entry point and a single exit point-subject to precedence, latency, and resource constraints. Solving the problem exactly is known to be difficult, and most compilers use a greedy list scheduling algorithm coupled with a heuristic. The heuristic is usually hand-crafted, a potentially time-consuming process. In contrast, we present a study on automatically learning good heuristics using techniques from machine learning. In our study, a recently proposed optimal basic block scheduler was used to generate the machine learning training data. A decision tree learning algorithm was then used to induce a simple heuristic from the training data. The automatically constructed decision tree heuristic was compared against a popular critical-path heuristic on the SPEC 2000 benchmarks. On this benchmark suite, the decision tree heuristic reduced the number of basic blocks that were not optimally scheduled by up to 55% compared to the critical-path heuristic, and gave improved performance guarantees in terms of the worst-case factor from optimality.

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Section: Introductionmentioning

confidence: 99%

Learning heuristics for basic block instruction scheduling

et al. 2007

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“…Traditionally, instruction scheduling has been employed by compilers to exploit instruction level parallelism in straight-line code in the form of basic blocks [Heffernan and Wilken 2005; and superblocks [Heffernan et al 2006;Shobaki and Wilken 2004;. In this section we review the different approaches towards solving the spatial scheduling problem.…”

Section: Related Workmentioning

confidence: 99%

A constraint programming approach for integrated spatial and temporal scheduling for clustered architectures

Beg

Beek

2013

TECS

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Many embedded processors use clustering to scale up instruction level parallelism in a cost effective manner. In a clustered architecture, the registers and functional units are partitioned into smaller units and clusters communicate through register-to-register copy operations. Texas Instruments, for example, has a series of architectures for embedded processors which are clustered. Such an architecture places a heavier burden on the compiler, which must now assign instructions to clusters (spatial scheduling), assign instructions to cycles (temporal scheduling), and schedule copy operations to move data between clusters. We consider instruction scheduling of local blocks of code on clustered architectures to improve performance. Scheduling for space and time is known to be a hard problem. Previous work has proposed greedy approaches based on list scheduling to simultaneously perform spatial and temporal scheduling, and phased approaches based on first partitioning a block of code to do spatial assignment and then performing temporal scheduling. Greedy approaches risk making mistakes that are then costly to recover from and partitioning approaches suffer from the well-known phase ordering problem. In this paper, we present a constraint programming approach for scheduling instructions on clustered architectures. We employ a problem decomposition technique that solves spatial and temporal scheduling in an integrated manner. We analyze the effect of different hardware parameters-such as the number of clusters, issue-width and inter-cluster communication cost-on application performance. We found that our approach was able to achieve an improvement of up to 26%, on average, over a state-of-the-art technique on superblocks from SPEC 2000 benchmarks.

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“…Clearly, the number of cycles depends on the quality of the scheduling algorithm, and most of all on the two-dimensional layout that provides communication channels for the qubits. To extract the physical communication resources for low-level networks such as level-1 error correction, we have employed the QPOS scheduling tool , which is based on traditional compiler scheduling heuristics [Chekuriet al 1996;Deitrich and Hwu 1996;Shobaki and Wilken 2004], and has demonstrated better circuit schedules than carefully hand-optimized layouts. In this manner, we can extrapolate that fully serialized error correction at level 2 will last approximately 0.3 seconds, which is two orders of magnitude longer than the time to error correct at level 1.…”

Section: Logical Qubit Design and Cost Of Error Correctionmentioning

confidence: 99%

High-level interconnect model for the quantum logic array architecture

Metodi

Thaker

Cross

et al. 2008

J. Emerg. Technol. Comput. Syst.

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We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

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Optimal Superblock Scheduling Using Enumeration

Abstract: The superblock is a scheduling region that is used by compilers for exploiting instruction-level

Cited by 23 publications

References 19 publications

Learning heuristics for basic block instruction scheduling

Learning heuristics for basic block instruction scheduling

A constraint programming approach for integrated spatial and temporal scheduling for clustered architectures

High-level interconnect model for the quantum logic array architecture

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