Optimal synthesis of multichip architectures

Gebotys,

doi:10.1109/iccad.1992.279367

Cited by 30 publications

(11 citation statements)

References 8 publications

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“…Proposition 2 [4] Nodes with high power over delay ratio have to be assigned to lowervoltage resources to minimize the total power consumption under the time constraints in the multiple voltage synthesis.…”

Section: Proposition 1 [1] the Delay Of An Operation Is Inversely Promentioning

confidence: 99%

“…Gebotys and Elmasry incorporated a partitioning model into an integer programming formulation for high-level synthesis [4]. This formulation simultaneously performs partitioning, scheduling, and allocating and considers off-chip delays and off-chip buses, but does not model the effects of multiplexing, control or routing on area or performance.…”

Section: Introductionmentioning

confidence: 99%

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Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

Jiang

Selvaraj

2006

J Supercomput

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This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize the power consumption with resources operating at multiple voltages. The input to both schemes is an unscheduled data flow graph (DFG), and the timing or the resource constraints. In the paper, partitioning is considered with scheduling in the proposed algorithms as multiple voltage design can lead to an increase in interconnection complexity at layout level. That is, in the proposed algorithms power consumption is first reduced by the scheduling step, and then the partitioning step takes over to decrease the interconnection complexity. Both time-constrained and resource-constrained algorithms have time complexity of O(n 2 ), where n is the number of nodes in the DFG. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve the power reduction under timing constraints and resource constraints by an average of 46.5 and 20%, respectively.

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Section: Proposition 1 [1] the Delay Of An Operation Is Inversely Promentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

Jiang

Selvaraj

2006

J Supercomput

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“…There has been a significant works on spatial partitioning and synthesis. Early works in synthesis field [1,2] used scheduling and allocation of tasks to solve the spatial partitioning problem. In the literature, many methods have developed by different authors to solve the temporal partitioning problem.…”

Section: Introductionmentioning

confidence: 99%

Combining temporal partitioning and temporal placement techniques for communication cost improvement

Ouni

Ayadi

Mtibaa

2011

Advances in Engineering Software

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“…Interger Linear Programming (ILP) models of other partitioning and synthesis problems have been addressed by researchers. Simultaneous spatial partitioning and synthesis is formulated as an ILP by Gebotys in [106]. Niemann and Marwedel [108] present an ILP-based methodology for hardware software partitioning of co-design systems.…”

Section: Previous Workmentioning

confidence: 99%

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

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The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YY)October 2001 2. REPORT TYPE Approved for public release; distribution unlimited. SUPPLEMENTARY NOTES ABSTRACT (Maximum 200 Words)Synthesis and Partitioning for Adaptive and Reconfigurable Computing Systems (SPARCS) is a computer aided engineering environment for reconfigurable computers. SPARCS contains software implementations of a variety of methods and algorithms for various subproblems for automating the task of producing designs for multi-FPGA (Field Programmable Gate Array) based reconfigurable computers. The SPARCS system includes tools for temporal partitioning, spatial partitioning, high-level synthesis, physical design, and arbiter synthesis. This is a comprehensive report on the SPARCS project, describing various techniques developed for solving these problems. In addition, this report contains some experimental results demonstrating the effectiveness of the SPARCS tools. Reconfigurable processors consisting of a sea of uncommitted FPGAs offer the same performance advantages of custom computing while retaining the flexibility of general purpose instruction architectures. In 1996, at the begining of this project, it was predicted that in near future reconfigurable processors can offer lOOx performance improvement over contemporary microprocessors, and 10-100x reduction in power/gate, 20x progress in density, and l,000,000x reduction in reconfiguration time compared to current reconfigurable devices.Unfortunately, state-of-the-art design synthesis methodologies were able to use perhaps 50-75% of the available gates at 30-50% of the maximum clocking rate of single reprogrammable device and were woefully inadequate in synthesizing multi-device systems. In order to deliver the performance expectations of reconfigurable architectures, dramatic improvements in the synthesis tools were necessary in both directions: (1) ability to synthesize to multiple device architectures, and, (2) improvement in utilization and delivered performance of each device. The goal of this project was to develop a coherent design synthesis and partitioning environment for co...

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Optimal synthesis of multichip architectures

Cited by 30 publications

References 8 publications

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

Combining temporal partitioning and temporal placement techniques for communication cost improvement

Computer Aided Engineering for Reconfigurable Computing (CAERC)

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