Optimal Test Structures for the Characterization of Integrated Transformers at mm-wave frequencies using the Open/Thru De-embedding Technique

Lauritano, Mario; Baumgartner, Peter

doi:10.1109/icmts50340.2022.9898235

Cited by 2 publications

(1 citation statement)

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“…The reason is that, for the smallest devices like DUT1, the total gate capacitance C gg of the transistor is smaller or comparable to the pad capacitance C pad ∼ 25 fF, which results in a large numerical error in the open de-embedding step. This phenomenon can be also observed simulating the deembedding process using an approach similar to that of [24]. Based on these considerations, a large value of M should be used if the width of the transistor is small.…”

Section: Capacitor-like Structuresmentioning

confidence: 76%

Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors

2023

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The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16 nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios.

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Section: Capacitor-like Structuresmentioning

confidence: 76%

Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors

2023

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Test Structures for the Characterization of the Gate Resistance in 16nm FinFET RF Transistors

Lauritano¹,

Baumgartner²

2023

Preprint

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The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios

show abstract

Optimal Test Structures for the Characterization of Integrated Transformers at mm-wave frequencies using the Open/Thru De-embedding Technique

Cited by 2 publications

References 0 publications

Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors

Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors

Test Structures for the Characterization of the Gate Resistance in 16nm FinFET RF Transistors

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