Optimal Useful Clock Skew Scheduling In the Presence of Variations Using Robust ILP Formulations

Nawale,; Chen, Guihai

doi:10.1109/iccad.2006.320101

Cited by 9 publications

(11 citation statements)

References 14 publications

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“…Furthermore, few skew domains implemented in reliable manners are preferred in multi-domain clock skew scheduling [3], which could be formulated in the mixed integer linear programming form with limited quantitative factors [4]:…”

Section: Multi-domain Clock Skew Schedulingmentioning

confidence: 99%

“…In the literature, there are two ways to follow: physical location-aware clock skew scheduling [4,5,7] and clock skew scheduling-aware placement [8].…”

Section: Introductionmentioning

confidence: 99%

“…It is mainly based on the assumption that all delays in data paths are fixed, and its variants [1][2][3][4] are most studied in the condition where the timing relations are extracted and calculated from an existing circuit layout.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Register relocation to optimize clock network for multi-domain clock skew scheduling

Yang

Fan

Cong

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Multi-domain clock skew scheduling provides performance improvement for circuits in an efficient way. However, the cost of clock network construction could be further reduced when clock scheduling scheme is considered during placement. Here we focus on this and propose an incremental register relocation algorithm to minimize the distance to the nearby ones in the same skew domain, while registers are relocated within their permissible displacement range so as not to violate timing constraints. The experiments showed our method achieved a significant cost reduction in clock networks, which did NOT rely on any specified clock structures and was applicable to general clock constructions.

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Section: Multi-domain Clock Skew Schedulingmentioning

confidence: 99%

“…In the literature, there are two ways to follow: physical location-aware clock skew scheduling [4,5,7] and clock skew scheduling-aware placement [8].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Register relocation to optimize clock network for multi-domain clock skew scheduling

Yang

Fan

Cong

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…With theoretical guarantee, this technique enables us to specify a tradeoff parameter controlling the probability of constraint violation which is strongly related to timing yield. Such an approach has also been successfully used in [10] for clock scheduling. In our approach, we sample the subcircuits for simulations and use the results to decide the tradeoff parameter.…”

Section: A Linear Programming Formulationmentioning

confidence: 99%

Unified adaptivity optimization of clock and logic signals

Hu¹

2007

2007 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-VLSI design is increasingly sensitive to variations which often degrade the parametric yield. Post-silicon tuning techniques can compensate for specific variations on the die and thus significantly improve the yield. Previous works on adaptivity optimization for post-silicon tuning focus on either logic signal tuning or clock signal tuning. This paper proposes the first unified adaptivity optimization on logical and clock signal tuning, which enables us to significantly save resource. In addition, it does not need any assumption on variation distributions.Our unified optimization is based on a novel linear programming formulation which can be efficiently solved by an advanced robust linear programming technique. Due to the discrete nature of the problem, the continuous solution obtained from linear programming is then efficiently discretized. This procedure involves binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation. Our experimental results demonstrate that up to 50% area cost reduction can be obtained by the unified optimization compared to optimization on logic or clock alone. In addition, the proposed discretization approach significantly outperforms the alternatives in terms of solution quality and runtime.

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“…Targeting global zero skew not only costs in area and power, but also limits the achievable operating frequency to the maximum data path delay in the circuit. This has led to a paradigm shift from skew minimization to useful skew optimization as the latter has the potential to significantly improve design performance [4]- [9].…”

Section: Introductionmentioning

confidence: 99%

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure

Roy

Mattheakis²,

Masse-Navette³

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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With aggressive technology scaling and complex design scenarios, timing closure has become a challenging and tedious job for the designers. Timing violations persist for multi-corner, multi-mode designs in the deep-routing stage although careful optimization has been applied at every step after synthesis. Useful clock skew optimization has been suggested as an effective way to achieve design convergence and timing closure. Existing approaches on useful skew optimization: 1) calculate clock skew at sequential elements before the actual tree is synthesized and 2) do not account for the implementability of the calculated schedules at the later stages of design cycle. In this paper, we propose a novel clock tree resynthesis methodology which is based on a skew scheduling engine which works on an already built clock tree. The output of the engine is a set of positive and negative offsets which translate to the delay and accelerations, respectively in clock arrival at the clock tree pins. We demonstrate the effectiveness of the offsets at the output pins of the leaf-level clock drivers in comparison to the traditional clock scheduling in the clock pins of the flip-flops due to the better implementability and lesser area overhead and present an algorithm to accurately realize these offsets in the clock tree. Experimental results on large-scale industrial designs demonstrate that our clock tree resynthesis methodology achieves respectively 57%, 12%, and 42% average improvement in total negative slack, worst negative slack, and failure-end-point with an average overhead of 26% in clock tree area. We also experimentally study the impact of on-chip-variation-derates on our approach in terms of the timing metric improvement and clock tree overhead.Index Terms-Clock skew scheduling, clock tree synthesis (CTS), engineering change order (ECO), multi-corner, multi-mode (MCMM), useful skew.

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Optimal Useful Clock Skew Scheduling In the Presence of Variations Using Robust ILP Formulations

Cited by 9 publications

References 14 publications

Register relocation to optimize clock network for multi-domain clock skew scheduling

Register relocation to optimize clock network for multi-domain clock skew scheduling

Unified adaptivity optimization of clock and logic signals

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure

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