Optimal voltage allocation techniques for dynamically variable voltage processors

Kwon, Woocheol; Kim, Taewhan

doi:10.1109/dac.2003.1218855

Cited by 4 publications

(5 citation statements)

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“…A naive implementation of the offline optimum algorithm for deadline feasibility YDS [16] runs in time O(n 3 ). Faster implementations for discrete and continuous speeds can be found in [11,13,14]. [2] considered the problem of finding energy-efficient deadline-feasible schedules on multiprocessors.…”

Section: Other Related Resultsmentioning

confidence: 99%

“…In the problem introduced in [16] the QoS objective was deadline feasibility, and the objective was to minimize the energy used. To date, this is the most investigated speed scaling problem in the literature [2,6,3,9,11,12,14,16,17]. In this problem, each job i has a release time r i when it arrives in the system, a work requirement w i , and a deadline d i by which the job must be finished.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule

Bansal¹,

Chan

Pruhs

et al. 2009

Automata, Languages and Programming

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. (2012). Improved bounds for speed scaling in devices obeying the cube-root rule. Theory of Computing, 8(9), 209-229. DOI: 10.4086/toc.2012.v008a009 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract: Speed scaling is a power management technology that involves dynamically changing the speed of a processor. This technology gives rise to dual-objective scheduling problems, where the operating system both wants to conserve energy and optimize some Quality of Service (QoS) measure of the resulting schedule. In the most investigated speed scaling problem in the literature, the QoS constraint is deadline feasibility, and the objective is to minimize the energy used. The standard assumption is that the processor power is of the form s α where s is the processor speed, and α > 1 is some constant; α ≈ 3 for CMOS based processors. In this paper we introduce and analyze a natural class of speed scaling algorithms that we call qOA. The algorithm qOA sets the speed of the processor to be q times the speed that the optimal offline algorithm would run the jobs in the current state. When α = 3, we show that qOA is 6.7-competitive, improving upon the previous best guarantee of 27 achieved by the algorithm Optimal Available (OA). We also give almost matching upper and lower bounds for qOA for general α. Finally, we give the first non-trivial lower bound, namely e α−1 /α, on the competitive ratio of a general deterministic online algorithm for this problem.

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Section: Other Related Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule

Bansal¹,

Chan

Pruhs

et al. 2009

Automata, Languages and Programming

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“…Building on this, [24] combines the techniques of [23,34] to develop an optimal algorithm for the setting of discrete speeds and arbitrary release times. [27] further improved on this setting, giving an algorithm with runtime of O(kn log n) where k is the number of discrete speeds.…”

Section: Real-time Scheduling Contributionsmentioning

confidence: 99%

On the Complexity of Speed Scaling

Barcelo

Kling

Nugent

et al. 2015

Mathematical Foundations of Computer Science 2015

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It seems to be a corollary to the laws of physics that, all else being equal, higher performance devices are necessarily less energy efficient than lower performance devices. Conceptually there is an energy efficiency spectrum of design points, with high performance and low energy efficiency on one end, and low performance and high energy efficiency on the other end. As in most technologies, there is not a universal sweet spot for computer chips that is best for all situations. For example, there are situations when there are critical tasks to be done, when performance is more important than energy efficiency, and there are situations when there are no critical tasks, when energy efficiency may be more important than performance.Speed-scalable processors aim to resolve this conflict by allowing the operating system to dynamically choose the performance to energy trade-off. The resulting optimization problems involve scheduling jobs on such a processor and have conflicting dual objectives of quality of service and some energy related objective. This engenders many different optimization problems, depending on how one models the processor, the performance objective, and how one handles the dual objectives.In this thesis we map out a reasonably full landscape of all possible formulations, determining which assumptions drive computational tractability. Beyond identifying the individual computational complexities, we use algorithmics as a lens to study the combinatorial structure of such trade-off schedules. In particular, we give several general reductions which, in some sense, reduce the number of problems that are distinct in a complexity theoretic sense. We show that some problems, for which there are efficient algorithms on a fixed speed processor, are NP-hard. Finally, we present several primal-dual based polynomial time algorithms.iii 8 Let j be the green job. The set Ψ j := { 3, 4 } corresponds to the 2 execution intervals of j. The speeds at the border of the first execution interval, s ,3,j and s r,3,j , are both equal to s 2 . Similarly, the border speeds in the second execution interval, s ,4,j and s r,4,j , are both equal to s 1 . The value q ,j = 3 refers to the first and q r,j = 4 to the last execution interval of j. Finally, the indicator variables for j in the depicted example have the following values: y r,j (3) = y ,j (3) = 1 (borders at some release time), y r,j (4) = y ,j (4) = 0 (borders not at some release time), χ j (3) = 1 (not j's last execution interval), and χ j (4) = 0 (last execution interval of j). in the design process a car designer has to select a sweet spot on this spectrum as a design goal. There is seldom a uniquely defined sweet spot that is best for all situations, which is why both sports cars and economy cars are produced.Although information technology is no exception to this corollary, unlike other technologies, historically the sweet spot was invariably skewed towards the high performance low energy efficiency end of the spectrum. Energy consumption was simply not a first ...

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“…Regarding the speed choice model, only few theoretical works address the discrete speed model which is computationally much more complex but more realistic; see, e.g. [13,16,17]. Most related to our investigations is the work by Aupy et al [3] that studies the problem of minimizing the energy consumption under a given mapping of tasks to cores, and where the power consumed by a core running at speed s is equal to s α .…”

Section: Introductionmentioning

confidence: 99%

Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice

Simon¹,

Falk²,

Megow³

et al. 2019

Preprint

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Static (offline) techniques for mapping applications given by task graphs to MPSoC systems often deliver overly pessimistic and thus suboptimal results w.r.t. exploiting time slack in order to minimize the energy consumption. This holds true in particular in case computation times of tasks may be workload-dependent and becoming known only at runtime or in case of conditionally executed tasks or scenarios. This paper studies and quantitatively evaluates different classes of algorithms for scheduling periodic applications given by task graphs (i.e., DAGs) with precedence constraints and a global deadline on homogeneous MPSoCs purely at runtime on a per-instance base. We present and analyze algorithms providing provably optimal results as well as approximation algorithms with proven guarantees on the achieved energy savings. For problem instances taken from realistic embedded system benchmarks as well as synthetic scalable problems, we provide results on the computation time and quality of each algorithm to perform a) scheduling and b) voltage/speed assignments for each task at runtime. In our portfolio, we distinguish as well continuous and discrete speed (e.g., DVFS-related) assignment problems. In summary, the presented ties between theory (algorithmic complexity and optimality) and execution time analysis deliver important insights on the practical usability of the presented algorithms for runtime optimization of task scheduling and speed assignment on MPSoCs.

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Optimal voltage allocation techniques for dynamically variable voltage processors

Cited by 4 publications

References 8 publications

Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule

Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule

On the Complexity of Speed Scaling

Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice

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