Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates

Jaeger, B. De; Bonzom, Renaud; Leys, Frederik; Richard, Olivier; Steenbergen, Jan Van; Winderickx, G.; Moorhem, E. Van; Raskin, G.; Letertre, F.; Billon, T.; Meuris, Marc; Heyns, Marc

doi:10.1016/j.mee.2005.04.040

Cited by 108 publications

(72 citation statements)

References 4 publications

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“…After the p-well and channel implants, the Geon-Si wafer was passivated by growing a thin epi-Si layer (~1nm) which was then partially oxidised at room temperature in a water bath with ozone; see [4]. To avoid further oxidation, a thin layer of HfO 2 (~4nm) was then deposited by atomic layer deposition onto the SiO 2 before growing the TaN (~10nm) and next the TiN (~70nm) metal layers.…”

Section: Methodsmentioning

confidence: 99%

“…One of the drawbacks of Ge-based devices, however, relates to the poorer thermal oxide quality compared with that of Si, which has been found to give rise to a higher interface trap density [3]. Methods have been developed, therefore, to reduce this through Ge passivation [4]. One possible route for such passivation involves depositing an ultra-thin epitaxial Si layer on the surface of the Ge substrate which is then partially oxidised, prior to the growth of a high-k gate dielectric [4].…”

Section: Introductionmentioning

confidence: 99%

“…Methods have been developed, therefore, to reduce this through Ge passivation [4]. One possible route for such passivation involves depositing an ultra-thin epitaxial Si layer on the surface of the Ge substrate which is then partially oxidised, prior to the growth of a high-k gate dielectric [4]. Issues to be considered, however, relate to the uniformity of the Si/SiO 2 interface, as roughness can lead to carrier scattering, and also whether Ge segregation during growth of the epi-layer will affect passivation and consequently the interface trap density [5].…”

Section: Introductionmentioning

confidence: 99%

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TEM analysis of Si-passivated Ge-on-Si MOSFET structures for high performance PMOS device technology

Norris

Ross

Cullis

et al. 2010

J. Phys.: Conf. Ser.

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Abstract. In this paper, we present a transmission electron microscopy analysis of novel Geon-Si MOSFETs using a JEOL 2010F and an aberration-corrected JEOL 2200FSC. A key feature of these devices is the incorporation of a very thin (~1nm) Si passivation layer on top of the Ge virtual substrate, which is partially oxidised to form SiO 2 (~0.5nm) prior to depositing HfO 2 dielectric. We will show that the thin SiO 2 layer is not purely amorphous but has some degree of crystal ordering due to being bonded to crystalline materials. Moreover, we will examine the presence of small monolayer variation in Si/SiO 2 interface roughness.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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TEM analysis of Si-passivated Ge-on-Si MOSFET structures for high performance PMOS device technology

Norris

Ross

Cullis

et al. 2010

J. Phys.: Conf. Ser.

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“…4. It is found that, with GeO x ILs thicker than 0.5 nm, the superior MOS interfaces with D it as low as 1~2×10 11 cm -2 eV -1 can be realized for the Al 2 O 3 /GeO x /Ge structures. On the other hand, when the GeO x IL is thinner than 0.5 nm, the significant degradation of GeO x /Ge interface is found to occur, as seen in the increase of D it from 2 to 8×10 11 cm -2 eV -1 at the energy of E i -0.2 eV in Fig.…”

Section: Ge Gate Stack Technologiesmentioning

confidence: 98%

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

et al. 2011

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MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO 2 /Ge interfaces have been regarded as promising. However, these interfaces have still employed thick GeO 2 layers. Recently, we have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al 2 O 3 /GeO x /Ge gate stacks were fabricated by exposing the ALD Al 2 O 3 /Ge structures to ECR oxygen plasma and oxidizing the Ge surface through the very thin ALD Al 2 O 3 layer. We present our recent results of the interface properties using this interface. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer combined with an ECR sputtering SiO 2 or an ALD Al 2 O 3 gate insulator is shown to reduce D it down to low order of 10 11 cm -2 eV -1 . The physical origin of this D it reduction and the role of the nitridation are discussed.

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“…A key element is the gate stack consisting of a few monolayers of Si, a 0.5 nm SiO 2 and a 4 nm ALD HfO 2 . The thickness of the Si passivation layer, epitaxially grown on the Ge, has to be critically controlled as a too thin layer causes problems with the exposure of the Si-Ge interface during the oxidation and a too thick layer gives stress enhancing the density of interface states [23]. Figure 4 illustrates some cross-sectional TEM images of high-k gate stacks in Ge with different thickness of the Si passivation layer.…”

Section: Epitaxial Si As Passivation Layer For Ge Devicesmentioning

confidence: 99%

Electrical Defect Issues of Hetero-Epitaxy for Advanced Nanometric CMOS Technologies

Claeys

González²,

Eneman³

et al. 2009

ECS Trans.

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Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates

Cited by 108 publications

References 4 publications

TEM analysis of Si-passivated Ge-on-Si MOSFET structures for high performance PMOS device technology

TEM analysis of Si-passivated Ge-on-Si MOSFET structures for high performance PMOS device technology

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

Electrical Defect Issues of Hetero-Epitaxy for Advanced Nanometric CMOS Technologies

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