Optimised PLC power transfer on avionic DC Power Lines: Coupling circuit and lightning protection

Brison, M.; Bensetti, Mohamed; Lacerda, Raul de; Santos, Filipe Vinci dos; Taurand, C.

doi:10.1109/isplc.2017.7897110

Cited by 5 publications

(4 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In Ref. [67], the authors use the premise of the equal impedance matching method to design a PLC coupling circuit with an input filter and to obtain optimal signal power transfer at the PLC modem. For the complex conjugate matching case, the power reflection coefficient [59,68] can be expressed as…”

Section: Based On Matching Methodsmentioning

confidence: 99%

A Review of Impedance Matching Techniques in Power Line Communications

Wang

Cao

2019

Electronics

View full text Add to dashboard Cite

Impedance mismatch that degrades signal power transfer and affects communication reliability is a major obstacle for power line communications (PLC). Impedance matching techniques can be designed to effectively compensate for the impedance mismatch between PLC modems and power line networks at a specific frequency or for a given frequency band. In this paper, we discuss the tradeoffs that need to be made when designing an effective impedance matching network. We also make a comprehensive review of previous state-of-the-art PLC impedance matching techniques and provide a useful classification of each technique. Finally, we discuss important issues (concerns) and provide suggestions for research directions deserving more attention. This review provides a useful guideline for researchers and manufacturers to quickly understand impedance matching principles and facilitate the design of an effective impedance matching coupler for PLC applications.

show abstract

Section: Based On Matching Methodsmentioning

confidence: 99%

A Review of Impedance Matching Techniques in Power Line Communications

Wang

Cao

2019

Electronics

View full text Add to dashboard Cite

show abstract

“…The LS estimator is shown in (6), obtaining the corresponding estimatesĤ LSx for each transmitted symbol. Note that it is necessary to calculate the FFT of the received symbols r Cx [n], denoted as R Cx [k] in (6), where x = {0, 1} is the index of the corresponding CSS sequence. On the other hand, the FFT of the transmitted symbols C x [k] can be computed previously offline, and not necessarily at run time.…”

Section: Description Of the Channel Estimation And Equalizationmentioning

confidence: 99%

“…The block LS Estimator performs the FFT of the received symbols r Cx [n] and the product by the inverse of the transmitted symbols 1 Cx[k] , already computed offline, as described in (6).…”

Section: Description Of the Channel Estimation And Equalizationmentioning

confidence: 99%

Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution

2020

View full text Add to dashboard Cite

Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain realtime solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and the Zynq® UltraScale+ (US+) devices, by using a single-, dual-and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dualcore proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one in Zynq® US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.

show abstract

“…1 that the power line simultaneously transmits 50 Hz one-way electricity and 2-20 MHz noise signal, but only the noise signal is recorded. The coupling circuit, which enables to connect the measurement instrument to the 220 V power grid, is a second-order pass band filter equipped with appropriate protective components to filter power signal out [18,19]. The compliance of this circuit with EMC requirement was verified by immunity tests against surges and electrical fast transients.…”

Section: Measurement Setupmentioning

confidence: 99%