Optimised realisations of large integer multipliers and squarers using embedded blocks

Gao, Shuang; Chabini, Noureddine; Al-Khalili, D.; Langlois, J. M. Pierre

doi:10.1049/iet-cdt:20060074

Cited by 21 publications

(22 citation statements)

References 6 publications

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“…In [14], the authors present an efficient methodology for the implementation of multiplication and squaring functions for large unsigned integers. They propose a general architecture for the multiplier and squarer which are composed by using smaller symmetric multiplier blocks.…”

Section: Related Workmentioning

confidence: 99%

“…If the number of partial products in the first level is odd, the final partial product (the middle partial product) is considered in the next stage of addition. This strategy is applied at each level of the partial-product summation and is close to what is also used in [14] where the strategy is explored for summing partial-products for multipliers using symmetric (rather than asymmetric) embedded blocks. Similar to the previous strategy, the partial-products could be processed as a single whole block or be divided into top and bottom regions.…”

Section: Outside-inmentioning

confidence: 99%

“…Because Core Generator restricts generated multiplier sizes to 64 × 64 or smaller, these data points are only provided up to that point. Finally, we also implemented a symmetric multiplier generation method (Sym) [14] that treats each 24 × 17 multiplier as a 17 × 17 multiplier, and uses the diagonal partialproduct generation method described in section 5.2.The adder trees for the Sym multipliers were implemented using a strategy similar to the Outside-In Whole. Although this is clearly inefficient, the purpose of this particular baseline is to highlight the importance of considering asymmetry in multiplier generation.…”

Section: Comparison To Other Composable Multipliersmentioning

confidence: 99%

See 2 more Smart Citations

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

Srinath

Compton

2010

Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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The introduction of asymmetric embedded multiplier blocks in recent Xilinx FPGAs complicates the design of larger multiplier sizes. The two different input bitwidths of the embedded multipliers lead to two different shifting factors for the partial products that must be summed. This makes even the most straightforward multiplier design less intuitive. In this thesis, I present a methodology and set of equations to automatically generate Verilog hardware description code for arbitrary multiplier sizes composed of arbitrarily-sized asymmetric embedded multiplier cores. The presented technique also uses intelligent rearrangement of the multiplier block outputs into partial product terms to reduce the overall delay of the circuit. Multipliers created with this generator are faster and use fewer DSP blocks than either those created using Xilinx Core Generator or those created by simply using the '*' operator in Verilog. It also uses fewer LUTs than those created using the '*' operator. Finally, the presented generator can create multipliers larger than possible with Core Generator, and is limited only by the number of available embedded multipliers.4 Acknowledgement I would like to thank my advisor Katherine Compton for providing me the opportunity to pursue this research under her supervision. I thank her for the invaluable guidance and support she has extended throughout the duration of my degree.

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Section: Related Workmentioning

confidence: 99%

Section: Outside-inmentioning

confidence: 99%

Section: Comparison To Other Composable Multipliersmentioning

confidence: 99%

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Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

Srinath

Compton

2010

Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…Son yapılan büyük çarpıcı -kare alıcı ile ilgili çalışmalar, hızlı tasarım ve esneklik avantajlarından dolayı FPGA uygulamalarında yoğunlaşmıştır [6][7][8][9]. Tasarımlarda ayrıştırma yöntemi ile böl-fethet veya Karatsuba-Ofman çarpım algoritmaları kullanılmıştır.…”

Section: Introductionunclassified

FPGA’lar için Ardışık Büyük Tam Sayı Kare Alıcılar

Şentürk¹,

Gök²

2014

Çukurova Üniversitesi Mühendislik-Mimarlık Fakültesi Dergisi

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ÖzetBu çalışmada FPGA'lar için ardışık büyük tam sayı kare alıcı tasarımı gösterilmiştir. Tasarım boru hatlı yapıdadır ve çoğu modern FPGA'larda bulunan gömülü çarpıcıları kullanmaktadır. Tasarımda, geliştirdiğimiz ayrıştırma yöntemi ile gömülü çarpıcıların daha verimli kullanılması sağlanmıştır. Tasarım yarım veya tam büyüklükte sonuç üretebilmektedir. Sentez sonuçları, Ardışık Büyük Tam Sayı Kare Alıcı uygulamalarının, önceki çalışmalarda gösterilen ardışık büyük çarpıcılarla yaklaşık aynı kaynak tüketimine sahip olmasına rağmen, %62'ye varan yüksek performans kazançları sergilediğini göstermiştir.Anahtar Kelimeler: FPGA, Boru hatlı tasarım, Ardışık büyük kare alıcı Large Sequential Integer Squarers for FPGAs AbstractThis paper presents sequential large integer squarer designs for FPGAs. The design is pipelined and uses embedded multiplier blocks which exist in most modern FPGAs. More efficient use of embedded multipliers is provided with the decomposition method which we developed in the design. The design can generate a full size or a single size product. The syntheses results show that compared to sequential large multipliers presented in the previous researches, Sequential Large Integer Squarers consume almost same resources and have up to 62% higher performance.

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“…When realized using the STMicroelectronics (ST) 90 nm 1V CMOS standard cells library, the multiplier is ∼ 20% slower, consumes ∼ 70% more power and occupies ∼ 70% more silicon area. For this reason several efficient techniques have been proposed in the past for both ASIC [8][9][10][11][12][13][14][15] and FPGA-based [16] implementations of squaring circuits.…”

Section: Introductionmentioning

confidence: 99%

Fast‐squarer circuits using 3‐bit‐scan without overlapping bits

Perri

Corsonello

2010

Circuit Theory & Apps

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SUMMARYThis paper presents a novel technique to design fast-squaring circuits. The proposed approach speeds up squaring operations combining the 3-bit scan without overlapping bits and the folding technique.Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32-bit squarer exploiting the novel way of generating partial products reaches a 769 MHz running frequency, dissipates less than 19.3 mW on average and occupies ∼ 91 000 m 2 of silicon area.

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Optimised realisations of large integer multipliers and squarers using embedded blocks

Cited by 21 publications

References 6 publications

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

FPGA’lar için Ardışık Büyük Tam Sayı Kare Alıcılar

Fast‐squarer circuits using 3‐bit‐scan without overlapping bits

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