Optimising bandwidth over deep sub-micron interconnect

Abstract

In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies.

System level interconnect design for network-on-chip using interconnect IPs

“…The wiring delay of a distributed RC line can be modeled as: T is the wiring delay, l is the wire length, r is the resistance per unit length and c is the capacitance per unit length. This is a very good approximation and is reported to be accurate to within 4% for a very wide range of r and c [10]. Knowing the clock cycle time and RC delay model, the maximum resource size satisfies:…”

System level interconnect design for network-on-chip using interconnect IPs

“…This is a very good approximation and is reported to be accurate to within 4% for a very wide range of r and c [10]. Knowing the clock cycle time and RC delay model, the maximum resource size satisfies:…”

“…To model the crosstalk effects, the coupling capacitance is multiplied by this switch factor, which takes the value between 0 and 2 for the best and worst case respectively. In Figure 4, suppose that the victim line in the middle switches up from zero to one, the switching pattern that gives rise to the worst case delay on the victim line is when the two aggressor lines switch down from one to zero (almost) simultaneously [10]. The worst-case delay is then given by:…”

“…Using simulations, Dinesh [10] shows the optimal wire width and spacing with different constraints. For a total wire width of 15 µm, using copper wires with technology dependent constant Using real inverters with output impedance of a minimum sized inverter 7 kΩ, input capacitance of the same inverter 1 fF and optimal repeater insertion, maximum number of wires allowed (75) also gives the maximum total bandwidth on 20 Gbps.…”

Optimization of Chip Interconnect Area by using Interconnect Length and Width

“…Using fat wires which reduce delay, however, may reduce global interconnect bandwidth. In [20], interconnect width and spacing are simultaneously optimized for bandwidth, but no analytical expression for the optimal width and spacing is given, and the global interconnect delay is also not considered. For achieving large bandwidth and short latency simultaneously, the product of delay and bandwidth has been introduced as a figure of merit [21].However, the interconnect width, spacing, thickness and dielectric height are assumed to be equal and able to be arbitrarily varied in [21], which is not realistic because for a given technology and a given layer, the interconnect thickness and dielectric height cannot be changed.…”